A TDM NoC supporting QoS, multicast, and fast connection set-up

Stefan, Stefan; Molnos,; Ambrose,; Goossens,

doi:10.1109/date.2012.6176690

Cited by 25 publications

(17 citation statements)

References 30 publications

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“…Slot tables are placed in the network adapter and routing is done through message headers. In the latest version of aelite, called dAElite [12], the static routing tables are back in the routers to support multicast routing.…”

Section: Related Workmentioning

confidence: 99%

A light-weight statically scheduled network-on-chip

2012

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Abstract-This paper investigates how a light-weight, statically scheduled network-on-chip (NoC) for real-time systems can be designed and implemented. The NoC provides communication channels between all cores with equal bandwidth and latency. The design is FPGA-friendly and consumes a minimum of resources. We implemented a 64 core 16-bit multiprocessor connected with the proposed NoC in a low-cost FPGA.

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Section: Related Workmentioning

confidence: 99%

A light-weight statically scheduled network-on-chip

2012

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“…17 A lighter version that only provides guaranteed service was proposed to further simplify routers. 18,19 More recently, Stefan and Goossens proposed a modification to AEthearal that enables multipath routing, both static and dynamic (based on a true random number generator), to enhance security by using a nondeterministic path instead of the source-routing used in AEthearal. 20 In addition, the need for real-time worst-case execution time (WCET) analysis inspired a set of works, such as the T-Crest project (www.t-crest.org), which tries to build a time-predictable multicore for real-time applications.…”

Section: Noninterference In Nocsmentioning

confidence: 99%

Networks on Chip with Provable Security Properties

et al. 2014

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“…Each partition is exclusively allocated a set of DMA units and communication memories (CMEMs). The communication architecture is composable by making use of a composable Network on Chip (NoC) [15] and a composable memory controller [16]. Shared memory shown in Figure 1 can be an off-chip DDR memory or an on-chip SRAM memory.…”

Section: A Hardware Platformmentioning

confidence: 99%

Composable and Predictable Dynamic Loading for Time-Critical Partitioned Systems

Sinha

Koedam

Wijk

et al. 2014

2014 17th Euromicro Conference on Digital System Design

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Abstract-In time-critical systems such as in avionics, for safety and timing guarantees, applications are isolated from each other. Resources are partitioned in time and space creating a partition per application. Such isolation allows fault containment and independent development, testing and verification of applications. Current partitioned systems do not allow dynamically adding applications. Applications are statically loaded in their respective partitions. However dynamic loading can be useful or even necessary for scenarios such as on-board software updates, dynamic reconfiguration or re-loading applications in case of a fault. In this paper we propose a software architecture to dynamically create and manage partitions and a method for composable dynamic loading which ensures that loading applications do not affect the running applications and vice versa. Furthermore the loading time is also predictable i.e. the loading time can be bounded a priori. We achieve this by splitting the loading process into parts, wherein only a small part which reserves minimum required resources is executed in the system partition and the other parts are executed in the allocated application partition which ensures isolation from other applications. We implement the software architecture for a SoC prototype on an FPGA board and demonstrate its composability and predictability properties. I. INTRODUCTIONTime-critical systems such as in the avionics domain have strict safety, real-time and fault tolerance constraints. To ensure these constraints and for fault-containment, applications are isolated from each other at the cycle-level. That is applications cannot affect each other even by a single cycle. With temporal and spatial partitioning, faults in an application cannot affect the rest of the system and applications can be developed, tested and verified independently. Without isolation, each small change to an application, requires the system and all applications to be re-verified. Allocating dedicated hardware to achieve isolation has disadvantages of increased cost and weight, therefore integrated architectures with shared resources are proposed in avionics with Integrated Modular Avionics (IMA) [1]. In IMA, resources are partitioned in time and space to create logical containers for each application. For commercial deployment, avionics industry has standardized partitioning with the ARINC 653 API [2] and AIR (ARINC in Space RTOS) [3] standards.The aforementioned partitioned systems are static systems, wherein all applications are integrated at design-time. In standards such as ARINC653 and AIR, applications are statically loaded in their respective partitions and the system iterates through a static Time Division Multiplexed (TDM) schedule at run time [4]. They do not cope with dynamic aspects such as adding new applications at run-time or on-board application software updates or dynamic reconfiguration in case of a fault.Consider the example of a spacecraft. The operation plan of a spacecraft can be changed to deal with u...

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A TDM NoC supporting QoS, multicast, and fast connection set-up

Cited by 25 publications

References 30 publications

A light-weight statically scheduled network-on-chip

A light-weight statically scheduled network-on-chip

Networks on Chip with Provable Security Properties

Composable and Predictable Dynamic Loading for Time-Critical Partitioned Systems

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