A technique for simultaneously improving the product of cutoff frequency–breakdown voltage and thermal stability of SOI SiGe HBT

Abstract

The product of the cutoff frequency and breakdown voltage ( f T ×BV CEO ) is an important figure of merit (FOM) to characterize overall performance of heterojunction bipolar transistor (HBT). In this paper, an approach to introducing a thin N + -buried layer into N collector region in silicon-on-insulator (SOI) SiGe HBT to simultaneously improve the FOM of f T ×BV CEO and thermal stability is presented by using two-dimensional (2D) numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOI structure, the effects of SOI insulation layer thickness (T BOX ) on f T , BV CEO , and the FOM of f T ×BV CEO are presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces f T , slightly increases BV CEO to some extent, but ultimately degrades the FOM of f T ×BV CEO . Although the f T , BV CEO , and the FOM of f T ×BV CEO can be improved by increasing SOI insulator SiO 2 layer thickness T BOX in SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of SiO 2 layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick T BOX , a thin N + -buried layer is introduced into collector region to not only improve the FOM of f T ×BV CEO , but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N + -buried layer in collector region is investigated in detail. The result show that the FOM of f T ×BV CEO is improved and the device temperature decreases as the N + -buried layer shifts toward SOI substrate insulation layer. The approach to introducing a thin N + -buried layer into collector region provides an effective method to improve SOI SiGe HBT overall performance.

Thermal resistance matrix representation of thermal effects and thermal design of microwave power HBTs with two-dimensional array layout*

“…In recent years, heterojunction bipolar transistors (HBTs) array with parallel HBT cells layout has been used widely for microwave power applications [1][2][3][4] due to its high current handling capability. [5][6][7] However, the self-heating effect caused by the power dissipation of each HBT cell and the thermal coupling effect among the adjacent HBT cells result in an uneven temperature profile in the HBTs array. Because of the positive temperature coefficient of the emitter current, the central HBT cells with higher temperature will conduct more current and consequently generate more heat, which aggravates the thermal effects and leads to thermal breakdown or thermal runaway.…”

Thermal properties of transition-metal dichalcogenide

“…[14] Thermal management is an important issue for the design and application of electronic devices, which even is becoming a limiting factor currently to the device development. [15][16][17][18][19][20][21][22][23][24][25][26][27][28][29] Owing to the atomic thickness of monolayer TMDs, thermal management is more challenging in TMDs-based electronics. On one hand, highly localized Joule heating in their ultrathin confined space can easily create "hot spots".…”