A technique to reduce power and test application time in BIST

The testing power is the biggest VLSI chip testing as the testing power is ver functional power which affects the reliability paper low test power architecture is propose pattern in one scan chain serially and the re loaded parallel by the serial scan chain one a proposed technique is very effective in test p the serial shifting happens only in one scan ch the switching activity in other scan chains. Fro conducted on ISCAS89 benchmark circuits, th power architecture reduces the test powe additional test cycles. Index terms-Linear Feedback Shift Reg enable (SE), System on Chip (SoC).

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A technique to reduce power and test application time in BIST

Cited by 3 publications

References 6 publications

TOSCA: Total Scan Power Reduction Architecture based on Pseudo-Random Built-in Self Test Structure

TOSCA: Total Scan Power Reduction Architecture based on Pseudo-Random Built-in Self Test Structure

Test power aware STUMP BIST

Modified low power scan based technique

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