Modified low power scan based technique

Abstract

The testing power is the biggest VLSI chip testing as the testing power is ver functional power which affects the reliability paper low test power architecture is propose pattern in one scan chain serially and the re loaded parallel by the serial scan chain one a proposed technique is very effective in test p the serial shifting happens only in one scan ch the switching activity in other scan chains. Fro conducted on ISCAS89 benchmark circuits, th power architecture reduces the test powe additional test cycles. Index terms-Linear Feedback Shift Reg enable (SE), System on Chip (SoC).

Developments in scan shift power reduction: a survey

“…Though the fanout of the scan port of the cell is usually one and so redundant toggle on it during functional mode results in minimal additional power, the cell presented in [10] blocks it saving the additional power during functional operation. Special scan cell which can be used to save power during shift operation presented in [14]- [17]. Figure 1.…”