A template-based technique for efficient Clifford+T-based quantum circuit implementation

Biswal, Laxmidhar; Das, Rakesh; Bandyopadhyay, Chandan; Chattopadhyay, Anupam; Rahaman, Hafizur

doi:10.1016/j.mejo.2018.08.011

Cited by 26 publications

(6 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…For practical use, pattern-matching methods have been proposed that reduce the required number of gates by replacing partial circuits with smaller, logically equivalent circuits [58][59][60][61]. It is also effective to realize specific gates with fewer CNOT gates.…”

Section: Gate Decompositionmentioning

confidence: 99%

ISAAQ: Ising Machine Assisted Quantum Compiler

Naito¹,

Hasegawa²,

Matsuda³

et al. 2023

Preprint

View full text Add to dashboard Cite

It is imperative to compile quantum circuits for Noisy Intermediate-Scale Quantum (NISQ) devices because of the limited connectivity of physical qubits and the high error rates of gate operations. One of the most critical steps in quantum circuit compilation is qubit routing, an NP-Hard problem that involves placing and moving logical qubits to minimize compilation overhead. In this study, we propose ISing mAchine Assisted Quantum compiler (ISAAQ) to perform qubit routing with Ising machines, which can efficiently solve Quadratic Unconstrained Binary Optimization (QUBO) problems. ISAAQ accurately estimates the compilation costs by updating itself using previous compilation results, and accelerates qubit routing by solving QUBO problems in parallel with multiple Ising machines. In addition, ISAAQ exploits a cost-reduction method that implements commutative logical Controlled-NOT (CNOT) gates with fewer physical CNOT gates, which is particularly effective for planar devices when implementing original gates. Experimental results on both IBM QX5 and IBM QX20 show that ISAAQ outperforms the heuristic methods available in Qiskit and tket, as well as an existing QUBO method, requiring fewer physical CNOT gates for most benchmark circuits. ISAAQ performs particularly well on large circuits, demonstrating its strong scalability with respect to the number of logical CNOT gates.

show abstract

Section: Gate Decompositionmentioning

confidence: 99%

ISAAQ: Ising Machine Assisted Quantum Compiler

Naito¹,

Hasegawa²,

Matsuda³

et al. 2023

Preprint

View full text Add to dashboard Cite

show abstract

“… Equivalent circuit identities relating to switching of T ‐gate between the line as depicted in Ref. [29, Figure 3(f)] …”

Section: Proposed Techniquementioning

confidence: 99%

Fault‐tolerant quantum implementation of conventional decoder logic with enable input

Biswal

Mondal

Rahaman

2021

IET Circuits, Devices & Syst

Self Cite

View full text Add to dashboard Cite

Decoherence is the greatest obstacle to the physical realization of scalable quantum computer, jeopardises coherent superposition of the qubit, and makes qubit extremely fragile. Quantum Error Correction Code (QECC), and Fault-tolerant quantum computation collectively could protect qubit and improve scalability. On the other hand, the conventional logic circuit is no more useful in quantum computing due to much difference from quantum logic. However, quantum computer has to perform classical tasks which can be addressed by translating to its equivalent quantum algorithm. Herein, zerogarbage-based reversible and fault-tolerant quantum circuit for 1 : 2, and 2 : 4 Decoder with enable signal using Clifford + T-group are proposed. Further, the design approach to implement n : 2 n decoder on fault-tolerant quantum logic in linear T − depth is extended. Besides, performance parameters likely T − count, T − depth, and garbage output have been evaluated for n : 2 n decoder. This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

show abstract

“…The effect of intermediate representations on different graph-based methods, such as BDD, inverter graphs and majority inverter graphs, in terms of their usability in making efficient circuit realizations is presented in the work of [11]. Three representations for huge binary functions were compared in this work, and the authors found that BDD is better for small functions due to the compact circuits it generates compared with the other two representations, which showed better improvements in cost compared with BDD with a cost reduction reaching 39% on average.…”

Section: Related Workmentioning

confidence: 99%

Reversible Circuit Synthesis Time Reduction Based on Subtree-Circuit Mapping

2020

View full text Add to dashboard Cite

Several works have been conducted regarding the reduction of the energy consumption in electrical circuits. Reversible circuit synthesis is considered to be one of the major efforts at reducing the amount of power consumption. The field of reversible circuit synthesis uses a large number of proposed algorithms to minimize the overall cost of circuits synthesis (represented in the line number and quantum cost), with minimal concern paid for synthesis time. However, because of the iterative nature of the synthesis optimization algorithms, synthesis time cannot be neglected as a parameter which needs to be tackled, especially for large-scale circuits which need to be realized by cascades of reversible gates. Reducing the synthesis cost can be achieved by Binary Decision Diagrams (BDDs), which are considered to be a step forward in this field. Nevertheless, the mapping of each BDD node into a cascade of reversible gates during the synthesis process is time-consuming. In this work, we implement the idea of the subtree-based mapping of BDD nodes to reversible gates instead of the classical nodal-based algorithm to effectively reduce the entire reversible circuit synthesis time. Considering Depth-First Search (DFS), we convert an entire BDD subtree in one step into a cascade of reversible gates. A look-up table for all possible combinations of subtrees and their corresponding reversible gates has been constructed, in which a hash key is used to directly access subtrees during the mapping process. This table is constructed as a result of a comprehensive study of all possible BDD subtrees and considered as a reference during the conversion process. The conducted experimental tests show a significant synthesis time reduction (around 95% on average), preserving the correctness of the algorithm in generating a circuit realizing the required Boolean function.

show abstract

A template-based technique for efficient Clifford+T-based quantum circuit implementation

Cited by 26 publications

References 10 publications

ISAAQ: Ising Machine Assisted Quantum Compiler

ISAAQ: Ising Machine Assisted Quantum Compiler

Fault‐tolerant quantum implementation of conventional decoder logic with enable input

Reversible Circuit Synthesis Time Reduction Based on Subtree-Circuit Mapping

Contact Info

Product

Resources

About