A test structure for channel length engineering of NAND gates in standard cell library

Reliability analysis of NAND gates with modified channel length in series n-MOSFETs

“…Since primitive cells such as NANDINOR gates have series connected MOSFETs inherently, modification of channel length is effective in leakage reduction. Although we have proposed a channel length engineering technique for primitive cells in standard cell libraries optimizing the performance and leakage [4], reliability issues such as hot carrier injection (HCI) have been left to be analyzed. In this paper, characteristics of NANDs with modified L have been analyzed under voltage stress condition with a test structure of 90 nm CMOS ring oscillator.…”

“…In this paper, characteristics of NANDs with modified L have been analyzed under voltage stress condition with a test structure of 90 nm CMOS ring oscillator. connected n-MOSFETs has the largest V DS of 1.0 V at input vector of (A, B, C) = (0,1,1), while the maximum VDS of N2 and N3 are less than that of NI by O.17 �0.19 V. Since it depends on V DS and channel length, subthreshold leakage current in NAND gates can be reduced by optimizing channel lengths of the series connected n-MOSFETs [4]. Although primitive cells are usually designed with the same minimum design rule, channel length engineering in standard cells can allow the leakage current reduction without significant increase of delay time.…”

“…Nl of series connected n-MOSFETs goes off state and rules the leakage current of odd-numbered stages, of which input signal is fixed to (0, 1, 1). The change ofLl from 0.10 to 0.11 f.!m has an effect on leakage current reduction by about 36 %, keeping the delay increase within 6% [4]. After voltage stress of V DD = Vstrs were applied to ROSe for stress time tstrso the evaluation parameters were measured for the reliability analysis.…”