A test time theorem and its applications

Venkataramani, Praveen; Sindia, Suraj; Agrawal, Vishwani D.

doi:10.1109/latw.2013.6562685

Cited by 7 publications

(10 citation statements)

References 30 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The implementation of similar experiments for chip test is in progress on Advantest T2000GS Automatic Test Equipment (ATE). Recent work shows that further reduction in test time is possible if an asynchronous test clock is used besides a properly selected voltage [23].…”

Section: Discussionmentioning

confidence: 99%

“…Methods have been proposed [8] [15] to vary the power supply during normal operation to reduce power dissipation. Voltage reduction can also be beneficial in power constrained testing [12], [22], [23]. Power managed scan architecture proposed in [12] uses the on-chip dual voltage regulator to reduce the supply voltage during scan shift in order to decrease the power dissipated.…”

Section: Prior Workmentioning

confidence: 99%

See 1 more Smart Citation

Finding best voltage and frequency to shorten power-constrained test time

Venkataramani

Sindia

Agrawal

2013

2013 IEEE 31st VLSI Test Symposium (VTS)

View full text Add to dashboard Cite

Abstract-In a digital test, supply voltage (VDD), clock frequency (ftest), peak power (PMAX ) and test time (T T ) are related parameters. For a given limit PMAX = PMAXfunc, normally set by functional specification, we find the optimum VDD = VDDopt and ftest = fopt to minimize T T . A solution is derived analytically from the technology-dependent characterization of semiconductor devices. It is shown that at VDDopt the peak power any test cycle consumes just equals PMAXfunc and ftest is fastest that the critical path at VDDopt will allow. The paper demonstrates how test parameters can be obtained numerically from MATLAB, or experimentally by bench test equipment like National Instruments' ELVIS. This optimization can cut the test time of ISCAS'89 benchmarks in 180nm CMOS into half.

show abstract

Section: Discussionmentioning

confidence: 99%

Section: Prior Workmentioning

confidence: 99%

Finding best voltage and frequency to shorten power-constrained test time

Venkataramani

Sindia

Agrawal

2013

2013 IEEE 31st VLSI Test Symposium (VTS)

View full text Add to dashboard Cite

show abstract

“…A synchronous test will then be just a special case. Leakage can be accounted for [20] but is neglected here for simplicity. Cycle energy is given by (1) and cycle power, which is the average power of a cycle, is P i = E i /T i .…”

Section: Test Timementioning

confidence: 99%

“…To make the matter worse, few test cycles that may consume two to four times the functional mode power, enforce a slow test clock [16], [21]. Aperiodic testing [17], [19], [20] can significantly reduce the test time. In this method, the test clock period is dynamically customized for each test clock cycle according to its power consumption.…”

mentioning

confidence: 99%

Few Good Frequencies for Power-Constrained Test

Gunasekar

Agrawal

2015

2015 28th International Conference on VLSI Design

Self Cite

View full text Add to dashboard Cite

In the aperiodic clock testing method, power is kept at the specified limit by stretching or contracting the clock periods according to circuit activity. As reported, the test time of power constrained test can be reduced by 40-50%. Considering the capability of the test equipment and simplicity of test program, the number of clock periods should be kept low. In this paper, we give algorithms to find the optimum clock periods. Using the well known relation that the test time equals total energy for the entire test divided by the average power, the kthroot solution maximizes the average power for k test clocks and given maximum power constraint. This solution uses a piece-wise linear approximation for the sorted pseudo-energy profile of test cycles obtained from power estimation and timing analysis tools. For small k, the kth-root solution is optimized by a numerically efficient locally exhaustive search (LES) algorithm. Results show that close to maximum attainable test time reduction is achievable by as few as four to ten selected clocks.

show abstract

“…The proposed method is then verified first through simulation and then experimentally on an Advantest T2000GS ATE. Although the research as it appears here has never been presented in entirety, parts have been displayed as posters [30], [32] or discussed at technical forums [5], [6], [31], [33], [34].…”

Section: Prior Workmentioning

confidence: 99%