A Thermal-Aware On-Line Fault Tolerance Method for TSV Lifetime Reliability in 3D-NoC Systems

Abstract

Through-Silicon-Via (TSV) based 3D Integrated Circuits (3D-IC) are one of the most advanced architectures by providing low power consumption, shorter wire length and smaller footprint. However, 3D-ICs confront lifetime reliability due to high operating temperature and interconnect reliability, especially the Through-Silicon-Via (TSV), which can significantly affect the accuracy of the applications. In this paper, we present an online method that supports the detection and correction of lifetime TSV failures, named IaSiG. By reusing the conventional recovery method and analyzing the output syndromes, IaSiG can determine and correct the defective TSVs. Results show that within a group, R redundant TSVs can fully localize and correct R defects and support the detection of R + 1 defects. Moreover, by using G groups, it can localize up to G × R and detect up to G × (R + 1) defects. An implementation of IaSiG for 32-bit data in eight groups and two redundancies has a worst-case execution time (WCET) of 5,152 cycles while supporting at most 16 defective TSVs (50% localization). By integrating IaSiG onto a 3D Network-on-Chip, we also perform a grid-search based empirical method to insert suitable numbers of redundancies into TSV groups. The empirical method takes the operating temperature as the factor of accelerated fault due to the fact that temperature is one of the major issues of 3D-ICs. The results show that the proposed method can reduce the number of redundancies from the uniform method while still maintaining the required Mean Time to Failure.

Impact of Temperature on Structure Deformation for Monolithic Inter-Tier vias In Monolithic 3D IC Packaging System

“…34 One more way of evaluating the reliability of a MIV structure is done by using mean time to failure (MTTF) parameter. The MTTF value is calculated by using Black's equation 5,31 = [ ] ( )…”

“…Another technical hurdle is the thermal management in 3D ICs which need to be addressed to improve the performance, reliability and lifetime of ICs. [3][4][5] In Ref. 6 authors have encapsulated cutting edge technologies in fabrication of TSVs and various interconnection methods involved in it.…”

Internal defect identification method of TSV 3D packaging based on built-in integrated sensor

“…The schematic diagram of the TSV 3D packaging structure is shown in Figure 1. 1–4 Since TSV gradually develops toward smaller sizes, the scale effect is more obvious and the stress mismatch is more serious, resulting in defects such as bottom voids, gaps and filling missing. 5–7 The existence of these defects can adversely affect the performance of electronic devices, reduce the reliability of the device, and even damage the device.…”

Compact TSV-Based Hairpin Bandpass Filter for Thz Applications

“…Fortunately, the through-silicon via (TSV) technology has been shown to be a good candidate for miniaturization and integration of passive devices [17][18][19][20][21][22][23][24]. TSV is a vital component of 3-D ICs [25-26, 29, 32], which can extend Moore's law for several more technology nodes despite the bottleneck of physical size transistor scaling [29].…”