A Thermal Simulation Process Based on Electrical Modeling for Complex Interconnect, Packaging, and 3DI Structures

Abstract

To reduce the product development time and achieve first-pass silicon success, fast and accurate estimation of very-large-scale integration (VLSI) interconnect, packaging and 3DI (3D integrated circuits) thermal profiles has become important. Present commercial thermal analysis tools are incapable of handling very complex structures and have integration difficulties with existing design flows. Many analytical thermal models, which could provide fast estimates, are either too specific or oversimplified. This paper highlights a methodology, which exploits electrical resistance solvers for thermal simulation, to allow acquisition of thermal profiles of complex structures with good accuracy and reasonable computation cost. Moreover, a novel accurate closed-form thermal model is developed. The model allows an isotropic or anisotropic equivalent medium to replace the noncritical back-end-of-line (BEOL) regions so that the simulation complexity is dramatically reduced. Using these techniques, this paper introduces the thermal modeling of practical complex VLSI structures to facilitate thermal guideline generation. It also demonstrates the benefits of the proposed anisotropic equivalent medium approximation for real VLSI structures in terms of the accuracy and computational cost.

Measurement and investigation of thermal properties of the on-chip metallization for integrated power technologies

“…Since the on-chip metallization of integrated technologies tends to be complex, having several layers and many vias, it is advantageous to use a thermally equivalent layer as a replacement in the numerical temperature simulation to reduce computing time and memory requirements, cf. also [5].…”

“…Thus, to prevent failures it is crucial to correctly assess the thermal behavior of the DMOS [1], [4], which is greatly influenced by the thermal conductivity and heat capacitance of the on-chip metallization. This holds especially true if thick power metal layers are used, but also applies to VLSI technologies [5].…”

Thermal-aware DC IR-drop co-analysis using non-conformal domain decomposition methods

“…The Joule heating effects become increasingly significant with the shrinking scale of the silicon process because of the increase of on-chip power density, inclusion of more metal layers with higher densities and the use of dielectric materials with lower thermal conductivities. Subsequently, the temperature effects on the electrical performance of the three-dimensional system should be carefully considered, as well in the electrical designs (Jiang et al 2010).…”