A Three-Dimensional Simulation Study of Source/Drain-Tied Double-Gate Fin Field-Effect Transistor Design for 16-nm Half-Pitch Technology Generation and Beyond

Abstract

This paper presents a three-dimensional (3D) simulation study of source/drain (S/D)-tied (SDT) double-gate (DG) fin field-effect transistor (FinFET) design for 16-nm half-pitch technology generation and beyond using technology computer-aided design (TCAD) tools. A simple process to fabricate the proposed SDT FinFET is proposed. An investigation of the fin width (W fin) on the electrical characteristics is shown, suggesting that a reduced W fin is good for both the suppression of short-channel effects and the reduction of parasitic capacitance in SDT FinFETs. Also, the self-heating can be well controlled in our proposed SDT FinFET which is a difficult task for SOI family. The proposed FinFET is also compared with the existing experimental data, showing that the SDT FinFET not only demonstrates desired short-channel characteristics due to its inherent structure advantages (partially insulating oxide under the channel region), but also reduces the costs of device fabrication due to its simple process method and planar-like structure.

Significance of Overdrive Voltage in the Analysis of Short-Channel Behaviors of n-FinFET Devices

“…The constant-current (CC) method [14] is used to extract the threshold voltage, V t , from the I ds −V gs plot (where I ds is the drain-to-source current and V gs is the gate-source voltage). In this work, we have selected 1 × 10 −8 A as the CC from [16]. Linear threshold voltage, V t,lin , is measured at a very low drain-source voltage, V ds , of 50 mV (or V ds,low ).…”

“…(Here, V SS is defined to be equal to V gs .) For V SS , we have selected a value which results in a tenfold increase of I ds from 1 × 10 −10 A to 1 × 10 −9 A in [16]. In [5], V DIBLSS = V DIBL + V SS represents the gate controllability over the channel.…”

Thermal analysis of self-heating in saddle MOSFET devices

“…1) To overcome SCEs on MOSFETs, three-dimensional (3D) structure field-effect transistors (FETs), such as FinFETs and saddle MOSFETs have been attracted growing interests as possible device structures beyond 30 nm 2) and various modeling and analysis were investigated with previous works. 3) The Saddle MOSFET including advantage of recessed channel array transistor (RCAT) and having the similar structure as FinFET was previously introduced. Saddle MOSFET has advantage such as excellent SCE immunity, high I on , low drain-induced barrier lowering (DIBL), excellent subthreshold swing (SS), nearly constant V th with the recess depth, and large process margin over conventional RCAT.…”