A three-terminal band-trap-band tunneling model for drain engineering and substrate bias effect on GIDL in MOSFET

Guo, Jung-Yi; Liu, Y.-C.; Chou, Ming Yueh; Wang, M.T.; Shone, F.

doi:10.1109/16.701483

Cited by 22 publications

(7 citation statements)

References 5 publications

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“…The contact currents are calculated by using Ramo-Shockley method. 13,14) Figure 1 shows the BTBT mechanisms including BTB tunneling 1) included in our Monte Carlo (MC) simulation. Figures 1(a In MC simulation, BTBT carriers with charge P c calculated by eqs.…”

Section: Simulation Methodsmentioning

confidence: 99%

“…Band-to-band tunneling (BTBT) has attracted tremendous attention as a crucial reason for gate-induced-drainleakage (GIDL) and hot-hole-injection (HHI), both, theoretically and experimentally. [1][2][3][4][5][6] BTBT occurring in the gate-to-drain overlap region in the presence of high electric field in a metal-oxide-semiconductor field-effect-transistor (MOSFET), results in drain leakage current. However, up to date, many simulation studies are based on the driftdiffusion or hydrodynamics models as a generation-recombination term which is not suitable to the nano-scale MOSFETs in which non-equilibrium transport is dominant.…”

Section: Introductionmentioning

confidence: 99%

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Monte Carlo Simulation of Band-to-Band Tunneling in Silicon Devices

Xia

Song

et al. 2007

jjap

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A band-to-band tunneling model including trap-assisted tunneling has been implemented in our ensemble full band Monte Carlo simulator. Four kinds of band-to-band tunneling mechanisms are taken into account. All the parameters in the band-toband tunneling model are verified by comparing the pn junction reverse current with the experimental data. Then, gateinduced-drain-leakage currents caused by band-to-band tunneling in a 45 nm gate length n-metal-oxide-semiconductor fieldeffect-transistor are investigated. Results indicate that band-to-band tunneling can cause additional hot holes which becomes an important issue for the device reliability. Moreover, The gate-induced-drain-leakage currents caused by band-to-band tunneling in parallel with Si/SiO 2 interface and normal to Si/SiO 2 interface are compared. The influence of drain voltage on the two components of the gate-induced-drain-leakage currents is considered.

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Section: Simulation Methodsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Monte Carlo Simulation of Band-to-Band Tunneling in Silicon Devices

Xia

Song

et al. 2007

jjap

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“…The GIDL is more in case of single-diffused drain as compared to double-diffused drain. At low subtract voltage the minority carrier accumulated into drain depletion region under the gate region that forms the path for the GIDL current [32] [33]. Further the GIDL current increases exponential with thinner gate oxide thickness, low-V TH and the higher potential difference between gate and drain [34] [35].…”

Section: Gate-induced Drain Leakagementioning

confidence: 99%

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

Bikki¹,

Karuppanan²

2017

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Low power supply operation with leakage power reduction is the prime concern in modern nano-scale CMOS memory devices. In the present scenario, low leakage memory architecture becomes more challenging, as it has 30% of the total chip power consumption. Since, the SRAM cell is low in density and most of memory processing data remain stable during the data holding operation, the stored memory data are more affected by the leakage phenomena in the circuit while the device parameters are scaled down. In this survey, origins of leakage currents in a short-channel device and various leakage control techniques for ultra-low power SRAM design are discussed. A classification of these approaches made based on their key design and functions, such as biasing technique, power gating and multi-threshold techniques. Based on our survey, we summarize the merits and demerits and challenges of these techniques. This comprehensive study will be helpful to extend the further research for future implementations.

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“…W . The higher body potential reduces the hot-holes generated during drain disturb and thus increases the drain disturb time [7,8].…”

Section: Process Descriptionmentioning

confidence: 99%

“…W . The higher body potential reduces the hot-holes generated during drain disturb and thus increases the drain disturb time [7,8].The endurance characteristics for the SO1 and bulk CMOS cells are compared in Figure 5. The SO1 cell demonstrates less window closure than the bulk CMOS cell.…”

mentioning

confidence: 99%

An advanced flash memory technology on SOI

Burnett

Shum²,

Baker³

International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217)

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For the first time, EEPROM functionality is demonstrated on double-poly bitcells on SO1 using the same layout as standard bulk CMOS bitcells. By using FN tunneling for program and erase (PE) operations, the P E characteristics of the floating-body SO1 bitcell are comparable to the bulk CMOS characteristics. Bitcell endurance for SO1 cells show significantly less window closure than bulk CMOS cells. High-voltage SO1 device characteristics are also compared with bulk devices. With sufficient body contacts, the high-voltage SO1 devices can support the required bitcell voltages.LOCOS-based isolation for bulk and a modified PBL isolation for SO1 [5]. The bitcell has a tunnel oxide of 95A and an equivalent ONO thickness of I8OA. Figures I(a) and l(b) show SEM cross-sections along the bitline and wordline of a SO1 bitcell array. As seen in the figures, the body of the bitcell is completely floating as it uses the same layout as a standard bulk CMOS bitcell. The high-voltage devices have a 240A gate oxide thickness and use a hard arsenic S/D with a phosphorus co-implant. SO1 high-voltage devices were fabricated with final silicon thicknesses of l d and 1.5kA for comparison with bulk CMOS devices. BITCELL CHARACTERISTICS INTRODUCTIONBecause of the improved performance and reduced power consumption achievable with SO1 technology, a significant effort has been focused on SO1 development resulting in functional DRAMS, SRAMs, microcontroller cores, and microprocessor cores on SO1 [l-41. However, for general embedded applications and future system-on-achip solutions, Flash EEPROM functionality must be offered. Despite the tremendous circuit achievements on RAM and logic circuits, no one has demonstrated even a functional NVM bitcell on SO1 using a conventional double-poly process. In this work, we report on the functionality of double-poly NVM bitcells fabricated on SOI. Because of the large voltages required to provide electrical programming and erasure, the peripheral highvoltage (HV) devices must support the required voltages. Due to the decreased breakdown voltages of SO1 HV NMOS transistors, special source-body tie devices are utilized to significantly improve the breakdown voltages. PROCESS DESCRIPTIONThe SO1 devices were fabricated on SIMOX substrates with 1 . 5 d final silicon thickness and a 4 d buried oxide. The memory cell for both SO1 and bulk CMOS is a selfaligned one-transistor flash EEPROM based on an embedded 0.4p.m double-poly CMOS technology with Fowler-Nordheim (FN) tunneling is utilized for program and erase operations, similar to that of the DINOR cell [6]. For programming, the bitcell is written to the low state by tunneling electrons from the floating gate to the drain which underlaps the gate. Single-device breakdown would be a likely problem with conventional hot-carrier programming. As shown in Figure 2, the program characteristics for the floating-body cell are identical to that of the bulk CMOS bitcell. For erasure, the bitcell is written to the high-state by tunneling electrons from the channel to ...

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A three-terminal band-trap-band tunneling model for drain engineering and substrate bias effect on GIDL in MOSFET

Cited by 22 publications

References 5 publications

Monte Carlo Simulation of Band-to-Band Tunneling in Silicon Devices

Monte Carlo Simulation of Band-to-Band Tunneling in Silicon Devices

SRAM Cell Leakage Control Techniques for Ultra Low Power Application: A Survey

An advanced flash memory technology on SOI

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