A threshold voltage model of short-channel fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs with high-
                    <i>k</i>
                    dielectric

Saramekala, Gopi Krishna; Dubey, Sarvesh; Tiwari, Pramod Kumar

doi:10.1088/1674-1056/24/10/108505

Cited by 4 publications

(3 citation statements)

References 29 publications

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“…Under this background, the ultra-thin body siliconon-insulator (UTB SOI) technology offers an attractive platform to develop a scalable and hybrid quantum computing system. [9][10][11][12] Enhanced analog/digital performance of 28 nm UTB SOI technology down to liquid helium temperature (4.2 K) for quantum computing has been demonstrated experimentally. [13,14] However, the design of CMOS qubitcontrol circuits at cryogenic temperatures is a difficult task, since the physical modeling of cryogenic temperature MOS-FETs operation is not so fully developed due to the sophisticated physics at 4.2 K compared to room temperature.…”

Section: Introductionmentioning

confidence: 99%

Role of remote Coulomb scattering on the hole mobility at cryogenic temperatures in SOI p-MOSFETs*

Zhang¹,

Chang²,

Du³

et al. 2020

Chinese Phys. B

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The impacts of remote Coulomb scattering (RCS) on hole mobility in ultra-thin body silicon-on-insulator (UTB SOI) p-MOSFETs at cryogenic temperatures are investigated. The physical models including phonon scattering, surface roughness scattering, and remote Coulomb scatterings are considered, and the results are verified by the experimental results at different temperatures for both bulk (from 300 K to 30 K) and UTB SOI (300 K and 25 K) p-MOSFETs. The impacts of the interfacial trap charges at both front and bottom interfaces on the hole mobility are mainly evaluated for the UTB SOI p-MOSFETs at liquid helium temperature (4.2 K). The results reveal that as the temperature decreases, the RCS due to the interfacial trap charges plays an important role in the hole mobility.

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Section: Introductionmentioning

confidence: 99%

Role of remote Coulomb scattering on the hole mobility at cryogenic temperatures in SOI p-MOSFETs*

Zhang¹,

Chang²,

Du³

et al. 2020

Chinese Phys. B

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“…Continuous scaling of traditional metal-oxide-semiconductor field-effect transistors (MOSFETs) for high performance can result in a rapid increase of power, which blocks its applications in the low power domains. [1][2][3] Therefore, tunnel field effect transistors (TFETs) have been considered as one of the most promising candidates for MOSFETs beyond 45 nm for future ultra-low power applications due to their better immunity to short channel effects, higher I ON /I OFF ratio, and so on. [4][5][6][7] However, TFETs to date show a low drain current due to the low band-to-band tunneling (BTBT) efficiency.…”

Section: Introductionmentioning

confidence: 99%

Analytical threshold voltage model for strained silicon GAA-TFET

Kang¹,

Hu²,

Wang³

2016

Chinese Phys. B

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Tunnel field effect transistors (TFETs) are promising devices for low power applications. An analytical threshold voltage model, based on the channel surface potential and electric field obtained by solving the 2D Poisson's equation, for strained silicon gate all around TFETs is proposed. The variation of the threshold voltage with device parameters, such as the strain (Ge mole fraction x), gate oxide thickness, gate oxide permittivity, and channel length has also been investigated. The threshold voltage model is extracted using the peak transconductance method and is verified by good agreement with the results obtained from the TCAD simulation.

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“…[8][9][10][11][12][13] Recently, the Re-S/D SOI MOSFETs have been analyzed in great detail. [8][9][10][11][12][13] Considering the variability problem of threshold voltage owing to the random dopant fluctuation in the doped channel, the back-gate bias is one of the unique features of devices for the ultimate tuning of threshold voltage even after the device has been fabricated. 14,15 The effects of back-gate bias voltage on the threshold voltage of FD SOI MOSFETs have been studied in detail.…”

Section: Introductionmentioning

confidence: 99%

An Analytical Threshold Voltage Model of Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFETs with Back-Gate Control

Saramekala

Tiwari

2016

Journal of Elec Materi

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This paper presents an analytical threshold voltage model for back-gated fully depleted (FD), recessed-source drain silicon-on-insulator metal-oxide-semiconductor field-effect transistors (MOSFETs). Analytical surface potential models have been developed at front and back surfaces of the channel by solving the two-dimensional (2-D) Poisson's equation in the channel region with appropriate boundary conditions assuming a parabolic potential profile in the transverse direction of the channel. The strong inversion criterion is applied to the front surface potential as well as on the back one in order to find two separate threshold voltages for front and back channels of the device, respectively. The device threshold voltage has been assumed to be associated with the surface that offers a lower threshold voltage. The developed model was analyzed extensively for a variety of device geometry parameters like the oxide and silicon channel thicknesses, the thickness of the source/drain extension in the buried oxide, and the applied bias voltages with back-gate control. The proposed model has been validated by comparing the analytical results with numerical simulation data obtained from ATLASä, a 2-D device simulator from SILVACO.

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A threshold voltage model of short-channel fully-depleted recessed-source/drain (Re-S/D) SOI MOSFETs with high- k dielectric

Cited by 4 publications

References 29 publications

Role of remote Coulomb scattering on the hole mobility at cryogenic temperatures in SOI p-MOSFETs*

Role of remote Coulomb scattering on the hole mobility at cryogenic temperatures in SOI p-MOSFETs*

Analytical threshold voltage model for strained silicon GAA-TFET

An Analytical Threshold Voltage Model of Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFETs with Back-Gate Control

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