A TiAl2O5 nanocrystal charge trap memory device

Abstract

A charge trapping memory device using Ti0.2Al0.8Ox film as charge trapping layer and amorphous Al2O3 as the tunneling and blocking layers was fabricated for nonvolatile memory application. TiAl2O5 nanocrystals are precipitated from the phase separation of Ti0.2Al0.8Ox film annealed at 900 °C. A memory window of 2.3 V and a stored electron density of 1×1013/cm2 were obtained. Good retention characteristics of the memory device at 80 °C were observed due to the deep charge trapping level as identified by the valence band offsets and electron energy loss spectrum measurements.

Metal-Insulator-Metal Single Electron Transistors with Tunnel Barriers Prepared by Atomic Layer Deposition

“…It appears reasonable that over time the Ti layer at the bottom of Ti/Pt island reacted with the ALD layer and altered the tunnel barriers, most likely leading to a formation of an insulating ternary Ti x Al y O compound. This observation is consistent with reports on ternary Ti x Al y O compounds [18,19], where a 1000-fold increase of resistance as compared to TiO 2 and a dielectric constant of 62 was reported. Such a large dielectric constant results in a charging energy smaller than k B T and attenuates gate modulation so that CBOs disappear.…”

Improved Memory Characteristics by NH3Post Annealing for ZrO2Based Charge Trapping Nonvolatile Memory

“…The charge loss was 11.6%, 5.7% and 4% up to 4×104s, for the three samples at 25℃, respectively. In order to predict the charge retention characteristics for a long time, according to the changing trend of the last three experimental data, we extrapolated the last two data, and supposed that the trend of charge loss fits a linear relation with the logarithm of retention time, up to ten years [6,9]. The extrapolation of the experimental results shows that the charge losses after ten years were 41.2%, 18% and 12.8%, respectively, suggesting that the NH 3 and N 2 annealing treatment could reduce the charge loss.…”

“…However, using Si 3 N 4 charge trapping layer in a SONOS structure leads to poor retention, due to the shallow traps, and the small conduction band offset at the Si 3 N 4 /tunneling layer interface [3]. Employing high-k dielectrics as the charge trapping layer to improve memory characteristics in SONOS structure has been reported by many researchers [4][5][6][7][8][9]. The high-k charge trapping layer allows a higher electric field cross the tunneling layer, due to electric flux density continuity [3], and results in a modified Fowler-Nordheim tunneling, due to the smaller conduction band offset (CBO) with a Si substrate [10].…”

The effect of the thickness of tunneling layer on the memory properties of (Cu2O)0.5(Al2O3)0.5 high-k composite charge-trapping memory devices

“…[8][9][10][11][12][13][14][15][16][17][18][19][20] To achieve good memory characteristics, some highk oxide dielectrics have been proposed and studied as the tunneling layer, chargetrapping layer and blocking layer, respectively. For example, HfO 2 , ZrO 2 , Y 2 O 3 and La 2 O 3 have been employed to replace Si 3 N 4 in SONOS memory devices to acquire better trapping characteristics, [21][22][23] and Al 2 O 3 has been employed as the tunneling layer and the blocking layer to reduce the working voltage.…”