A tightly-coupled multi-core cluster with shared-memory HW accelerators

Dehyadegari, Masoud; Marongiu, Andrea; Kakoee, Mohammad Reza; Benini, Luca; Mohammadi, Siamak; Yazdani, Naser

doi:10.1109/samos.2012.6404162

Cited by 13 publications

(14 citation statements)

References 10 publications

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“…Cong et al [10] also tackle the utilization wall by developing a heterogeneous multi-core architecture with shared-memory accelerators; their HW IPs communicate by means of shared L2 caches, accessible through NoC nodes. Previous work by our group (Burgio et al [8], Dehyadegari et al [16,17], Conti et al [11]) considers a tightly-coupled multi-core based on RISC32 cores sharing a L1 scratchpad and extend it with hardware processing units (HWPUs). HWPUs are managed by the software through an OpenMPbased programming model designed to mix parallelization and acceleration.…”

Section: Related Workmentioning

confidence: 99%

“…As we extend the STMicroelectronics P2012 cluster with tightly L1-coupled HW accelerators, our architectural template is similar to that used in Burgio et al [8] and Dehyadegari et al [17], but in our case it was implemented in a real, complete many-core platform. Moreover, contrarily to previous work in this category of accelerators, we propose a full-fledged flow that allows fast design exploration of heterogeneous clusters, with semi-automatic generation of HWPEs and estimation of power and area consumption based on RTL synthesis results.…”

Section: Related Workmentioning

confidence: 99%

“…In He-P2012, the tightly-coupled clusters are augmented with a set of HW accelerators that communicate with PEs via the same shared L1 data memory (a scratchpad) used by the PEs themselves. These tightly-coupled shared memory HW Processing Elements or HWPEs [17] address the shortcomings of more traditional copy-based accelerator models, such as the necessity to transfer and maintain coherent multiple copies of data between distinct processor and accelerator memory spaces. In addition, they diminish the semantic gap between executing a task in SW or HW: from a programming perspective, dispatching a HW task on a HW IP is not different from calling a SW function to perform the same task.…”

Section: He-p2012: Heterogeneous P2012mentioning

confidence: 99%

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He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores

Conti

Marongiu

Pilkington

et al. 2015

J Sign Process Syst

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The end of Dennardian scaling in advanced technologies brought about new architectural templates to overcome the so-called utilization wall and provide Moore's Law-like performance and energy scaling in embedded SoCs. One of the most promising templates, architectural heterogeneity, is hindered by high cost due to the design space explosion and the lack of effective exploration tools. Our work provides three contributions towards a scalable and effective methodology for design space exploration in embedded MC-SoCs. First, we present the He-P2012 architecture, augmenting the state-of-art STMicroelectronics P2012 platform with heterogeneous shared-L1 coprocessors called HW processing elements (HWPE). Second, we propose a novel methodology for the semi-automatic definition and instantiation of shared-memory HWPEs from a C source, supporting both simple and structured data types. Third, we demonstrate that the integration of HWPEs can provide significant performance and energy efficiency benefits on a set of benchmarks originally developed for the homogeneous P2012, achieving up to 123x speedup on the accelerated code region (∼98 % of Amdahl's law limit) while saving 2/3 of the energy.

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Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: He-p2012: Heterogeneous P2012mentioning

confidence: 99%

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He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores

Conti

Marongiu

Pilkington

et al. 2015

J Sign Process Syst

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“…Similarly to [23], Dehyadegari et al [13] introduce hardware processing units (HWPUs), which are tightly coupled to a cluster of general-purpose SPARC-V8 cores through a low-latency shared data memory. Burgio et al [9] refer to a similar architecture and focus on the programming model to support it.…”

Section: Related Workmentioning

confidence: 99%

“…In this work we propose an architecture for integrating HW accelerators into a tightly-coupled cluster, communicating through the shared data memory, as shown in Figure 1 [23] [13]. Tightly coupled shared-memory HW accelerators try to address the shortcomings of more traditional copybased accelerator models, such as the necessity to transfer and maintain coherent multiple copies of data between distinct processor and accelerator memory spaces.…”

Section: Introductionmentioning

confidence: 99%

Synthesis-friendly techniques for tightly-coupled integration of hardware accelerators into shared-memory multi-core clusters

Conti¹,

Marongiu²,

Benini³

2013

2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

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Several many-core designs tackle scalability issues by leveraging tightly-coupled clusters as building blocks, where lowlatency, high-bandwidth interconnection between a small/medium number of cores and L1 memory achieves high performance/watt. Tight coupling of hardware accelerators into these multicore clusters constitutes a promising approach to further improve performance/area/watt. However, accelerators are often clocked at a lower frequency than processor clusters for energy efficiency reasons. In this paper, we propose a technique to integrate shared-memory accelerators within the tightly-coupled clusters of the STMicroelectronics STHORM architecture. Our methodology significantly relaxes timing constraints for tightly-coupled accelerators, while optimizing data bandwidth. In addition, our technique allows to operate the accelerator at an integer submultiple of the cluster frequency. Experimental results show that the proposed approach allows to recover up to 84% of the slow-down implied by reduced accelerator speed.

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StreamDrive: a Dynamic Dataflow Framework for Clustered Embedded Architectures

Stoutchinin

Benini

2018

J Sign Process Syst

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In this paper, we present StreamDrive, a dynamic dataflow framework for programming clustered embedded multicore architectures. StreamDrive simplifies development of dynamic dataflow applications starting from sequential reference C code and allows seamless handling of heterogeneous and applicationspecific processing elements by applications. We address issues of efficient implementation of the dynamic dataflow runtime system in the context of constrained embedded environments, which have not been sufficiently addressed by previous research. We conducted a detailed performance evaluation of the StreamDrive implementation on our Application Specific MultiProcessor (ASMP) cluster using the Oriented FAST and Rotated BRIEF (ORB) algorithm typical of image processing domain. We have used the proposed incremental development flow for the transformation of the ORB original reference C code into an optimized dynamic dataflow implementation. Our implementation has less than 10% parallelization overhead, near-linear speedup when the number of processors increases from 1 to 8, and achieves the performance of 15 VGA frames per

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A tightly-coupled multi-core cluster with shared-memory HW accelerators

Cited by 13 publications

References 10 publications

He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores

He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores

Synthesis-friendly techniques for tightly-coupled integration of hardware accelerators into shared-memory multi-core clusters

StreamDrive: a Dynamic Dataflow Framework for Clustered Embedded Architectures

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