He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores

Conti, Francesco; Marongiu, Andrea; Pilkington, Chuck; Benini, Luca

doi:10.1007/s11265-015-1056-7

Cited by 4 publications

(3 citation statements)

References 37 publications

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“…Hardware Processing Elements: PULP clusters can be enhanced with application-specific accelerators, called Hardware Processing Elements (HWPE) [21], to deliver higher levels of performance and energy efficiency for specific tasks. Unlike many accelerator designs HWPEs do not necessarily rely on an external DMA to feed them with input data and extract output data, and they are not tied to a single core.…”

Section: B the Pulp Project And Heromentioning

confidence: 99%

A RISC-V-based FPGA Overlay to Simplify Embedded Accelerator Deployment

Bellocchi

Capotondi

Conti

et al. 2021

2021 24th Euromicro Conference on Digital System Design (DSD)

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Modern cyber-physical systems (CPS) are increasingly adopting heterogeneous systems-on-chip (HeSoCs) as a computing platform to satisfy the demands of their sophisticated workloads. FPGA-based HeSoCs can reach high performance and energy efficiency at the cost of increased design complexity. High-Level Synthesis (HLS) can ease IP design, but automated tools still lack the maturity to efficiently and easily tackle systemlevel integration of the many hardware and software blocks included in a modern CPS. We present an innovative hardware overlay offering plug-and-play integration of HLS-compiled or handcrafted acceleration IPs thanks to a customizable wrapper attached to the overlay interconnect and providing shared-memory communication to the overlay cores. The latter are based on the open RISC-V ISA and offer simplified software management of the acceleration IP. Deploying the proposed overlay on a Xilinx ZU9EG shows ≈ 20% LUT usage and ≈ 4× speedup compared to program execution on the ARM host core.

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Section: B the Pulp Project And Heromentioning

confidence: 99%

A RISC-V-based FPGA Overlay to Simplify Embedded Accelerator Deployment

Bellocchi

Capotondi

Conti

et al. 2021

2021 24th Euromicro Conference on Digital System Design (DSD)

Self Cite

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“…The ATU is a specialized component similar to the memory management unit (MMU) for processor cores. Differently from the MMU that uses a TLB to convert the addresses, the ATU design is customized for the specific data structure [34] and to guarantee that the translation does not introduce any Architecture of the ATU proposed in this paper and address decomposition.…”

Section: Generation Of the Plm Controllermentioning

confidence: 99%

System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip

Pilato

Mantovani

Guglielmo

et al. 2016

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In modern system-on-chip architectures, specialized accelerators are increasingly used to improve performance and energy efficiency. The growing complexity of these systems requires the use of system-level design methodologies featuring high-level synthesis (HLS) for generating these components efficiently. Existing HLS tools, however, have limited support for the system-level optimization of memory elements, which typically occupy most of the accelerator area. We present a complete methodology for designing the private local memories (PLMs) of multiple accelerators. Based on the memory requirements of each accelerator, our methodology automatically determines an areaefficient architecture for the PLMs to guarantee performance and reduce the memory cost based on technology-related information. We implemented a prototype tool, called MNEMOSYNE, that embodies our methodology within a commercial HLS flow. We designed 13 complex accelerators for selected applications from two recently-released benchmark suites (PERFECT and CORTEXSUITE). With our approach we are able to reduce the memory cost of single accelerators by up to 45%. Moreover, when reusing memory IPs across accelerators, we achieve area savings that range between 17% and 55% compared to the case where the PLMs are designed separately. Index Terms-Hardware accelerator, high-level synthesis (HLS), memory design, multibank architecture. I. INTRODUCTION S YSTEM-ON-CHIP (SoC) architectures increasingly feature hardware accelerators to achieve energy-efficient high performance [1]. Complex applications leverage these specialized components to improve the execution of selected computational kernels [2], [3]. For example, hardware accelerators for machine learning applications are increasingly used to identify underlying relations in massive unstructured data [4]-[6]. Many of these algorithms first build an internal model by analyzing very large data sets; then, they leverage Manuscript

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“…По скорости доступа к видеопамяти GPU также значительно превосходит CPU. Эффективная организация подсистемы памяти повышает общую эффективность графического процессора при работе с неграфическими задачами [5][6][7][8][9].…”

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Energy-efficient heterogeneous multiprocessor hardware and software complex

Leokhin¹,

Dvoretskiy²

2017

Izv. vysš. učebn. zaved., Priborostr.

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Обсуждаются вопросы использования гибридных, гетерогенных архитектур серверов, вычислительные модули которых состоят из универсальных процес-соров, программируемых логических интегральных схем и графических про-цессоров. Использование гетерогенной архитектуры позволяет повысить эф-фективность решения таких задач, как web-приложения, поиск и индексация больших массивов данных, хостинг физических и виртуальных серверов, мар-шрутизация, параллельные и "облачные" вычисления. Представлены результа-ты оценки эффективности ряда прикладных задач с параллельными вычисле-ниями -умножения матриц, операций с большими данными, поиска подстрок в потоке данных в режиме реального времени по шаблону. Описана архитекту-ра гетерогенного многопроцессорного аппаратно-программного комплекса, по-строенного на базе открытой телекоммуникационной платформы и стандарта microTCA/AMC, опытный образец которого изготовлен в рамках проекта "Раз-работка и организация высокотехнологичного производства энергоэффектив-ных многопроцессорных аппаратно-программных серверных комплексов для государственных и корпоративных информационных систем и центров обра-ботки данных". -контроль и видеонаблюдение -до 16 % (к 2020 г.); -данные, генерируемые встроенными системами -21 %; -пользовательские и мобильные данные -10 %; -метаданные и другая информация -53 %. Такая структура данных доказывает необходимость и актуальность повышения произ-водительности вычислительных систем. Одним из эффективных методов повышения произ-водительности вычислений является внедрение встроенных специализированных ресурсов, в результате чего вычислительная система становится гетерогенной.Использование гетерогенной архитектуры серверов, вычислительные модули которых состоят из универсальных процессоров (CPU), программируемых логических интегральных схем (ПЛИС) и графических процессоров (GPU), позволяет повысить эффективность реше-ния таких задач, как web-приложения, поиск и индексация больших массивов данных, хос-тинг физических и виртуальных серверов, маршрутизация, параллельные и "облачные" вы-числения.

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He-P2012: Performance and Energy Exploration of Architecturally Heterogeneous Many-Cores

Cited by 4 publications

References 37 publications

A RISC-V-based FPGA Overlay to Simplify Embedded Accelerator Deployment

A RISC-V-based FPGA Overlay to Simplify Embedded Accelerator Deployment

System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip

Energy-efficient heterogeneous multiprocessor hardware and software complex

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