A time-delay digital tanlock loop

Hussain, Zahir M.; Boashash, Boualem; Hassan-Ali, M.; Al-Araji, Saleh R.

doi:10.1109/78.934151

Cited by 56 publications

(20 citation statements)

References 9 publications

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“…Following similar approach to that in (Hussain et al, 2001) with a fixed-point analysis as in (Al-Araji et al, 2004) the locking range of the second-order TDTL, Figure 4, may be written as…”

Section: Tdtl Mathematical Analysismentioning

confidence: 99%

“…Later, this implementation issue was alleviated by the introduction of the time delay digital tanlock loop (TDTL) (Hussain et al, 2001;Al-Kharji Al-Ali et al, 2012b) However, the conventional TDTL has few shortcomings that limit its performance. These include the nonlinearity of the phase detector and the finite nonzero phase error in the locked state of the first-order TDTL system.…”

Section: Page 3 Of 29mentioning

confidence: 99%

“…Nonuniform DPPLs are more attractive due to the ease of their modelling and circuit implementation (Lindsey, 1981). The zero-crossing Digital phase-locked loop (ZCDPLL) and the DTL (Jae, and Chong, 1982;Hussain, Boashash, Hassan-Ali, and Al-Araji, 2001;Al-Araji, Al-Qutayri, and Al-Moosa, 2004;Al-Kharji Al-Ali et al, 2012a) are examples of the non-uniform DPLLs. The advantages of the DTL include good linearity and reduced sensitivity to variations in the power of the input signal.…”

Section: Page 3 Of 29mentioning

confidence: 99%

“…Therefore, a numerical solution using the fixed-point theorem (Best 2007;Hussain et al, 2001) can be used to solve the difference equation similar to the case of the ZC-DPLLs (Osborne,1980a(Osborne, ,1980b. The analyses for first-order and second-order TDTL systems are presented below.…”

Section: Tdtl Mathematical Analysismentioning

confidence: 99%

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Performance evaluation of the time delay digital tanlock loop architectures

Al-Ali

Anani

Al‐Qutayri

et al. 2015

International Journal of Electronics

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Performance evaluation of the time delay digital tanlock loop architecturesThis paper presents the architectures, theoretical analyses and testing results of modified time delay digital tanlock loops (TDTLs) systems. The modifications to the original TDTL architecture were introduced to overcome some of the limitations of the original TDTL and to enhance the overall performance of the particular systems. The limitations addressed in this paper include the nonlinearity of the phase detector, the restricted width of the locking range, and the overall system acquisition speed. Each of the modified architectures was tested through subjecting the system to sudden positive and negative frequency steps and comparing its response with that of the original TDTL. In addition, the performance of all the architectures was evaluated under noise-free as well as noisy environments.The extensive simulation results using MATLAB/SIMULINK demonstrate that the new architectures overcome the limitations they addressed and the overall results confirmed significant improvements in performance compared to the conventional TDTL system.

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Section: Tdtl Mathematical Analysismentioning

confidence: 99%

Section: Page 3 Of 29mentioning

confidence: 99%

Section: Page 3 Of 29mentioning

confidence: 99%

Section: Tdtl Mathematical Analysismentioning

confidence: 99%

See 2 more Smart Citations

Performance evaluation of the time delay digital tanlock loop architectures

Al-Ali

Anani

Al‐Qutayri

et al. 2015

International Journal of Electronics

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“…The proposed circuit is based on the digital phase lock loop (DPLL) which has been extensively used in communications and signal processing systems that require phase tracking and synchronization. 15,16 There are many types and forms of DPLLs, however, because sampling is a major operation in any DPLL, DPLLs are normally classified according to the nature of the sampling process they use as either uniform or non-uniform DPLLs. The non-uniform type of DPLLs offers better acquisition time and less circuit complexity compared to the uniform type, and hence attracted much of the research attention.…”

Section: Introductionmentioning

confidence: 99%

Synchronization of a Renewable Energy Inverter with the Grid

Anani¹,

Al-Ali²,

Ponnapalli³

et al. 2012

Sustainability in Energy and Buildings

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Probing bulk defect energy bands using generalized charge pumping method J. Appl. Phys. 111, 074501 (2012) Second and higher harmonics generation with memristive systems Appl. Phys. Lett. 100, 133109 (2012) Analysis of mid-range electric power transfer based on an equivalent circuit model J. Appl. Phys. 111, 07E733 (2012) The design, mathematical analysis, and testing results of the architecture of a new all-digital phase-locked loop system for synchronizing a voltage source DC-AC single-phase inverter with the low voltage utility grid are presented. The system which is based on the time-delay digital tanlock loop was simulated using MATLAB/ SIMULINK and was tested by subjecting the grid voltage to various perturbations similar to those which can occur in a real power system, such as voltage sags and nonlinear distortion of the grid voltage waveform. Results indicate that even in the presence of such perturbations the system achieved and/or re-gained synchronization within 100 ms. The proposed system is all-digital and can be readily implemented using a field programmable gate array and easily embedded into a power inverter. V C 2012 American Institute of Physics.

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Networks of coupled time-delay digital tanlock loops: chimeras and other emergent spatiotemporal dynamics

Paul¹,

Banerjee

2020

Nonlinear Dyn

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A time-delay digital tanlock loop

Cited by 56 publications

References 9 publications

Performance evaluation of the time delay digital tanlock loop architectures

Performance evaluation of the time delay digital tanlock loop architectures

Synchronization of a Renewable Energy Inverter with the Grid

Networks of coupled time-delay digital tanlock loops: chimeras and other emergent spatiotemporal dynamics

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