A Titanium Salicide Process Suitable for Submicron CMOS Applications

Abstract

This paper reports a titanium salicide process capable of fabricating low resistance salicide (<5 ohms/sq.) on narrow polysilicon leads (line widths less than 0.35 μm) which are heavily doped with arsenic and boron. The process utilizes conventional processing but avoids excessive vertical scaling of the titanium silicide film. The process has been demonstrated on a 0.35 μm CMOS technology and results show that a process window exists which is suitable for technologies of 0.35 μm and below. The most serious scaling issue for titanium salicide appears to be the silicide film thickness.