A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming

Lazzari, Cristiano; Anghel, Lorena; Reis, Ricardo

doi:10.1007/978-0-387-73661-7_21

Cited by 2 publications

(2 citation statements)

References 9 publications

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“…Legalization is the step where the cells are moved to eliminate overlapping. Detailed placement is the step where is done local placement optimizations with different goals: optimization of wire length, elimination of timing violations, reduction of power consumption, improvement of routability, and also manufacturability [14] [15]. The quality of the placement is fundamental to improving the routing quality.…”

Section: ) Placement Toolsmentioning

confidence: 99%

EDA: Overview and Some Trends

Reis¹

2022

JICS

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The development of any integrated circuit depends heavily on the quality of the EDA (Electronic Design Automation) tools used in the design flow. Improved CAD tools and algo-rithms are needed to cope with new fabrication technology requirements, advanced performance constraints, or simply the enormous number of elements involved. In this paper it is giving an overview of the importance of automation in the design process, and it is done a survey of different types of tools presenting some classifications of the tools. Then some few trends on EDA that are needed to deal with the evolution of manufacturing processes will be presented. Some optimi-zation techniques will be presented for selected physical de-sign problems (layout). An important aspect of the design is to reduce power consumption at all levels of abstraction. Power optimization is fundamental in nanoCMOS and in the IoT world. At logic and physical levels, one approach that can be used to optimize the circuit, especially reducing static leakage power and using the automatic generation of the cell layout. With on-the-fly cell generation, the same function can be implemented with a reduced number of transistors, requiring less area and significantly optimizing power and performance. Finally, the use of estimation and visualiza-tion tools is equally important. They can be applied either in the design flow or in the tool's development and research en-vironments as a way to observe and understand the behavior and interactions of algorithms and their operation on real designs and benchmarks.

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Section: ) Placement Toolsmentioning

confidence: 99%

EDA: Overview and Some Trends

Reis¹

2022

JICS

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“…Multiple placement algorithms perform horizontal positioning to achieve minimum-width cells. Stochastic algorithms like simulated annealing [3] or genetic algorithms [4] have been reported as placement solutions whose optimizations are limited by the stop conditions. Micro-cell layout formations for grouping sets of circuitry [5], [6] solve the placement and routing problem, but this do not create width-minimum standard cells.…”

Section: Introductionmentioning

confidence: 99%

Routing-Aware Standard Cell Placement Algorithm Applying Boolean Satisfiability

Duran

Roa

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Automatic standard cell layout generation employs algorithms for transistor folding, placing, and routing. Reported standard transistor placement algorithms neglect to consider, in advance, the full netlist and the routing to generate clean layouts.Here, we introduce a placement algorithm with an optimization for complete routing and pre-layout algorithm awareness. The algorithm applies pseudo-boolean satisfiability to determine the minimum-width transistors in the cell. Placement optimization provides route-awareness to circumvent routing congestion according to pins location. The proposed algorithm is implemented in a full automatic standard cell generation procedure, fulfilling a commercial 180nm technology node design rules. Final generated layouts are 30% more routable than the base SAT formulations, enabling 100% routing in complex cells.

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A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming

Cited by 2 publications

References 9 publications

EDA: Overview and Some Trends

EDA: Overview and Some Trends

Routing-Aware Standard Cell Placement Algorithm Applying Boolean Satisfiability

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