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In this work, we demonstrate the use of a nontraditional logic for the implementation of a dual-modulus prescaler. The proposed prescaler consumes less power than TSPC designs and is faster than ETSPC designs. The maximum speed reaches up to 96% of that of a single divide-by-2 D-flip-flop, the theoretical limit. Implemented in 130-nm CMOS technology, the maximum input frequency reaches 14.1GHz with a power consumption of 1.2mW.

This paper presents an improved methodology to automate the design and minimize the power consumption of typical CMOS OTAs. Using a geometric program formulation, this methodology can handle simultaneously several performance specifications including quiescent power, DC gain, unitygain bandwidth, CMRR and phase margin among others. We present some remarkable considerations, not detailed in literature, that arise when geometric programming is used for analog circuit design. In addition, some strategies to deal with related problems are presented. With these strategies a CAD tool to design three typical OTAs topologies has been developed. The tool gives the optimal values for all design variables and verifies the results with HSPICE simulations using level 49 BSIM3v3 models. The reported error between the performance predicted by the tool and the simulated performance is lower than 10% in the worst case. Measurement results for an OTA designed and fabricated in CMOS 0.35µm technology are presented. These results show that the design performed with the automated tool is silicon accurate, with relative error of 4% in the optimized specification.

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