Abstract-A 43-GHz wireless inter-chip data link including antennas, transmitters, and receivers is presented. The industry standard bonding wires are exploited to provide high efficiency and low-cost antennas. This type of antennas can provide an efficient horizontal communication which is hard to achieve using conventional on-chip antennas. The system uses binary amplitude shift keying (ASK) modulation to keep the design compact and power efficient. The transmitter includes a differential to single-ended modulator and a two-stage power amplifier (PA). The receiver includes a low-noise amplifier (LNA), pre-amplifiers, envelope detectors (ED), a variable gain amplifier (VGA), and a comparator. The chip is fabricated in 180-nm SiGe BiCMOS technology. With power-efficient transceivers and low-cost high-performance antennas, the implemented inter-chip link achieves bit-error rate (BER) around 10 8 for 6 Gb/s over a distance of 2 cm. The signal-to-noise ratio (SNR) of the recovered signal is about 24 dB with 18 ps of rms jitter. The transmitter and receiver consume 57 mW and 60 mW, respectively, including buffers. The bit energy efficiency excluding test buffers is 17 pJ/bit. The presented work shows the feasibility of a low power high data rate wireless inter-chip data link and wireless heterogeneous multi-chip networks.Index Terms-Bond-wire antenna, high-speed link, on-chip antenna, wirebond antenna, wireless inter-chip link, wireless transceiver.

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Blind zone in a phase-frequency detector (PFD) reduces the input detection range and aggravates cycle slips. This brief analyzes the blind zone in latch-based PFDs and proposes a technique that removes the blind zone caused by the precharge time of the internal nodes. With the proposed technique, the PFD achieves a small blind zone close to the limit imposed by process-voltage-temperature variations. The comparison between the proposed design and previous works is presented. Fabricated in a 130-nm CMOS technology, the measured blind zone is 61 ps, which is smaller than that of the existing topologies by almost 100 ps.

An ultra-low-power, low-voltage frequency synthesizer designed for implantable medical devices is presented. Several design techniques are adopted to address the issues in ultra-low voltage and current design. The charge pump (CP) in the synthesizer utilizes dynamic threshold-voltage and switch-coupled techniques to provide a high driving current with a low standby current. The synthesizer adopts a ring-based voltage controlled oscillator (VCO) that utilizes a dual resistor-varactor tuning technique to compensate for process-voltage-temperature (PVT) variations and the exponential voltage-to-current curve. Implemented in a 0.13-m CMOS technology, the 0.5-V medical-band frequency synthesizer consumes 440 W while exhibiting a phase noise of 91.5 dBc/Hz at 1-MHz frequency offset.Index Terms-Wireless implantable devices, low power, low voltage, PLL, MedRadio, low power electronics.

In this work, we demonstrate the use of a nontraditional logic for the implementation of a dual-modulus prescaler. The proposed prescaler consumes less power than TSPC designs and is faster than ETSPC designs. The maximum speed reaches up to 96% of that of a single divide-by-2 D-flip-flop, the theoretical limit. Implemented in 130-nm CMOS technology, the maximum input frequency reaches 14.1GHz with a power consumption of 1.2mW.