High-Speed Low-Power True Single-Phase Clock Dual-Modulus Prescalers

Chen, Wu-Hsin; Jung, Byunghoo

doi:10.1109/tcsii.2011.2106351

Cited by 38 publications

(30 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Unclassified

Order By: Relevance

“…The E-TSPC prescaler has the highest power consumption due to its short-circuit current. The maximum frequency of the proposed prescaler in the divide-by-2 mode is as fast as the prescaler based on Ref [2], but the power consumption is reduced by 30%. The proposed prescaler is about 20% faster than the prescaler based on Ref [2], and the power consumption is 15% less under the same operating frequency.…”

Section: Simulation Resultsmentioning

confidence: 97%

“…The power consumption versus the input frequency of the divide-by-2 circuit consisting of a single TSPC DFF, the proposed prescaler and the conventional prescaler based on [2,3,4] are simulated respectively as shown in Figs.3 a and b. The simulation results show that the conventional 2/3 prescaler can operate up to a maximum frequency of 4.5 GHz.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…When CK=0, the first inverter samples the input data D, the second inverter precharges the node P to high, and the third inverter holds the output. When CK turns from low to high, the first inverter holds the input data, the second stage evaluates the data where the node P is discharged if the input QB is low, and the third stage is the output stage that passes the evaluated data to the output [2]. The divide-by-2 is obtained by connecting the output QB to the input D of a single TSPC DFF.…”

Section: Architecturementioning

confidence: 99%

“…Several topologies are available for prescaler in the GHz range, including current-mode logic (CML), true single-phase clocked (TSPC) logic and extended TSPC (E-TSPC) logic [1]. Without the static power dissipation, the TSPC prescaler consumes lowest power among the three topologies [2]. With the scaling down of CMOS processes, the speed improvement of the transistors makes it possible to replace the CML logic in less than 10-GHz band applications.…”

Section: Introductionmentioning

confidence: 99%

“…With the scaling down of CMOS processes, the speed improvement of the transistors makes it possible to replace the CML logic in less than 10-GHz band applications. Various TSPC prescaler are proposed to improve the speed of TSPC prescaler with less power penalty, mainly focusing on reducing the critical path delay [2], minimizing the logic gates [3] and reducing the number of transistors stacking [4]. But there is a tradeoff between the power consumption and the speed in the conventional ones.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

A low-power high-speed true single phase clock divide-by-2/3 prescaler

Wang

et al. 2013

IEICE Electron. Express

View full text Add to dashboard Cite

Abstract:A novel low power high-speed true single-phase clockbased (TSPC) divide-by-2/3 prescaler is presented. By modifying the precharge branch in the TSPC flip-flop instead of the AND gate in conventional topologies, the inverter between the two flip-flops of the conventional divide-by-2/3 prescaler is eliminated, and the number of switching stages is reduced to 6. The prescaler is designed in SMIC 0.18 µm CMOS process, the simulating results show that the maximum operating frequency of the prescaler in divide-by-3 mode reaches 10 GHz with 1.836 mW power consumption, and is 50% faster than the conventional divide-by-3 circuit. The maximum operating frequency of the prescaler in divide-by-2 mode reaches 8 GHz with 1.34 mW power consumption.

show abstract

Section: Simulation Resultsmentioning

confidence: 97%

Section: Simulation Resultsmentioning

confidence: 99%

Section: Architecturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A low-power high-speed true single phase clock divide-by-2/3 prescaler

Wang

et al. 2013

IEICE Electron. Express

View full text Add to dashboard Cite

show abstract

High Speed-Low Power Divide-by-16/17 Dual Modulus Prescaler Using C2MOS

Chakraborty¹,

Agrawal²,

Gupta³

et al. 2016

Proceeding of International Conference on Intelligent Communication, Control and Devices

View full text Add to dashboard Cite

4.2 GHz 0.81 mW triple‐modulus prescaler based on true single‐phase clock

Jiang

2016

Electron. lett.

View full text Add to dashboard Cite

A dual-modulus prescaler based on true single-phase clock D flip-flop is presented. Instead of using the conventional digital logic circuit, the pass transistor logic circuit is applied to reduce the number of the transistors and the power of the divider. By adding only two additional transistors, a dual-modulus operation is achieved. Implemented in a standard 180 nm CMOS process, the proposed divide-by 6/7/8 prescaler based on the proposed dual-modulus one achieves an operating frequency of 4.2 GHz with a measured power consumption of 0.81 mW for a 1.2 V supply.

show abstract

High-Speed Low-Power True Single-Phase Clock Dual-Modulus Prescalers

Cited by 38 publications

References 7 publications

A low-power high-speed true single phase clock divide-by-2/3 prescaler

A low-power high-speed true single phase clock divide-by-2/3 prescaler

High Speed-Low Power Divide-by-16/17 Dual Modulus Prescaler Using C2MOS

4.2 GHz 0.81 mW triple‐modulus prescaler based on true single‐phase clock

Contact Info

Product

Resources

About