A signal generation system composed by a subharmonic VCO followed by an injection-locked frequency tripler (ILFT) is designed in a 0.25 µm BiCMOS SiGe:C technology. The ILFT implements a cascoded current-biased common emitter configuration that exploits the second harmonic of the VCO to enhance the efficiency in the generation of the injecting signal responsible for the ILFT locking. At 30.8 GHz, the system achieves a phase noise of -112 dBc/Hz at 1 MHz offset. The total current consumption is 38 mA for a supply voltage of 2.5 V.Index Terms-phase noise; millimeter wave frequency generation; subharmonic VCO; frequency tripler.

This paper presents an improved methodology to automate the design and minimize the power consumption of typical CMOS OTAs. Using a geometric program formulation, this methodology can handle simultaneously several performance specifications including quiescent power, DC gain, unitygain bandwidth, CMRR and phase margin among others. We present some remarkable considerations, not detailed in literature, that arise when geometric programming is used for analog circuit design. In addition, some strategies to deal with related problems are presented. With these strategies a CAD tool to design three typical OTAs topologies has been developed. The tool gives the optimal values for all design variables and verifies the results with HSPICE simulations using level 49 BSIM3v3 models. The reported error between the performance predicted by the tool and the simulated performance is lower than 10% in the worst case. Measurement results for an OTA designed and fabricated in CMOS 0.35µm technology are presented. These results show that the design performed with the automated tool is silicon accurate, with relative error of 4% in the optimized specification.

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