A transmitting circuit with adaptive calibration of output impedance for high speed interface

Abstract

A transmitting circuit for high-speed interface is proposed in this paper. Optimized 10-bit parallel to serial conversion and embedded output impedance calibration are used for enhancing the performance of this transmitting circuit. Designed with 0.18 μm CMOS, this transmitting circuit can achieve an output data rate of 1.5625 Gbps with 10-bit 156.25 MHz parallel input. The output amplitude of the current mode logic (CML) driver is 1.28 Vpp with a jitter of 24.3 ps. After adaptive calibration, the mismatch between output impedance and its expected value is within 0.5%. The active area of this entire transmitting circuit is 220.1 μm × 197.5 μm. With 1.8 V power supply, the power consumption of this transmitting circuit is 41.2 mW at 1.5625 Gbps data rate.