A transparent and adaptive reconfigurable system

Beck, Antonio Carlos Schneider; Rutzig, Mateus Beck; Carro, Luigi

doi:10.1016/j.micpro.2014.03.004

Cited by 23 publications

(6 citation statements)

References 54 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Runtime reconfigurability helps not only lower design cost but also increases flexibility, because the reconfigurable fabric can accommodate different custom instructions that can be switched on demand during runtime. While typically the RFUs are programmed with pregenerated configurations, the most sophisticated approaches currently studied in research, such as Dynamic Instruction Merging (DIM) [9], even shift the tasks of identifying and generating custom instructions to runtime with the goal to achieve transparent just-in-time acceleration.…”

Section: A Custom Instruction Set Extensionmentioning

confidence: 99%

Software/Hardware Co-Verification for Custom Instruction Set Processors

et al. 2021

View full text Add to dashboard Cite

Verification of software and processor hardware usually proceeds separately, software analysis relying on the correctness of processors executing machine instructions. This assumption is valid as long as the software runs on standard CPUs that have been extensively validated and are in wide use. However, for processors exploiting custom instruction set extensions to meet performance and energy constraints the validation might be less extensive, challenging the correctness assumption. In this paper we present a novel formal approach for hardware/software co-verification targeting processors with custom instruction set extensions. We detail two different approaches for checking whether the hardware fulfills the requirements expected by the software analysis. The approaches are designed to explore a tradeoff between generality of the verification and computational effort. Then, we describe the integration of software and hardware analyses for both techniques and describe a fully automated tool chain implementing the approaches. Finally, we demonstrate and compare the two approaches on example source code with custom instructions, using state-of-the-art software analysis and hardware verification techniques.

show abstract

Section: A Custom Instruction Set Extensionmentioning

confidence: 99%

Software/Hardware Co-Verification for Custom Instruction Set Processors

et al. 2021

View full text Add to dashboard Cite

show abstract

“…Built from arrays of Processing Elements (PEs) with programmable interconnects, RAs allow customized datapaths matching each different application's needs to be defined at run time. While traditionally requiring special compilers that can generate code to reconfigure the datapaths, RAs can also be coupled with run-time code mapping techniques that enable the transparent acceleration of already-deployed code without requiring any change in the software development process [Beck et al 2014].…”

Section: Problem Statement and Proposed Solutionmentioning

confidence: 99%

MuTARe: A Multi-Target, Adaptive Reconfigurable Architecture

Brandalero¹

2020

Anais Do Concurso De Teses E Dissertações Da SBC (CTD-SBC 2020)

Self Cite

View full text Add to dashboard Cite

With recent changes in transistor scaling trends, the design of all types of processing systems has become increasingly constrained by power consumption. At the same time, driven by the needs of fast response times, many applications are migrating from the cloud to the edge, pushing for the challenge of increasing the performance of these already power-constrained devices. The key to addressing this problem is to design application-specific processors that perfectly match the application's requirements and avoid unnecessary energy consumption. However, such dedicated platforms require significant design time and are thus unable to match the pace of fast-evolving applications that are deployed in the Internet-of-Things (IoT) every day. Motivated by the need for high energy efficiency and high flexibility in hardware platforms, this thesis paves the way to a new class of low-power adaptive processors that can achieve these goals by automatically modifying their structure at run time to match different applications' resource requirements. The proposed Multi-Target Adaptive Reconfigurable Architecture (MuTARe) is based upon a Coarse-Grained Reconfigurable Architecture (CGRA) that can transparently accelerate already-deployed applications, but incorporates novel compute paradigms such as Approximate Computing (AxC) and Near-Threshold Voltage Computing (NTC) to improve its efficiency. Compared to a traditional system of heterogeneous processing cores (similar to ARM's big.LITTLE), the base MuTARe architecture can (without any change to the existing software) improve the execution time by up to $1.3\times$, adapt to the same task deadline with $1.6\times$ smaller energy consumption or adapt to the same low energy budget with $2.3\times$ better performance. When extended for AxC, MuTARe's power savings can be further improved by up to $50\%$ in error-tolerant applications, and when extended for NTC, MuTARe can save further $30\%$ energy in memory-intensive workloads.

show abstract

“…In [23] the approach is applied to thread acceleration with multiple processors and one reconfigurable fabric. Beck et al [24] propose the Dynamic Instruction Merging (DIM) approach, which transparently maps, at runtime, sequences of basic blocks from a MIPS processor to a tightly coupled 2D CGRA. Inputs for the CGRA are fetched from the GPP's register file.…”

Section: Related Workmentioning

confidence: 99%

Transparent Acceleration of Program Execution using Reconfigurable Hardware

Paulino

Ferreira

Bispo

et al. 2015

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2015

View full text Add to dashboard Cite

The acceleration of applications, running on a general purpose processor (GPP), by mapping parts of their execution to reconfigurable hardware is an approach which does not involve program's source code and still ensures program portability over different target reconfigurable fabrics. However, the problem is very challenging, as suitable sequences of GPP instructions need to be translated/mapped to hardware, possibly at runtime. Thus, all mapping steps, from compiler analysis and optimizations to hardware generation, need to be both efficient and fast. This paper introduces some of the most representative approaches for binary acceleration using reconfigurable hardware, and presents our binary acceleration approach and the latest results. Our approach extends a GPP with a Reconfigurable Processing Unit (RPU), both sharing the data memory. Repeating sequences of GPP instructions are migrated to an RPU composed of functional units and interconnect resources, and able to exploit instruction-level parallelism, e.g., via loop pipelining. Although we envision a fully dynamic system, currently the RPU resources are selected and organized offline using execution trace information. We present implementation prototypes of the system on a Spartan-6 FPGA with a MicroBlaze as GPP and the very encouraging results achieved with a number of benchmarks.

show abstract

A transparent and adaptive reconfigurable system

Cited by 23 publications

References 54 publications

Software/Hardware Co-Verification for Custom Instruction Set Processors

Software/Hardware Co-Verification for Custom Instruction Set Processors

MuTARe: A Multi-Target, Adaptive Reconfigurable Architecture

Transparent Acceleration of Program Execution using Reconfigurable Hardware

Contact Info

Product

Resources

About