A true block pipelined programmable Reed-Solomon CODEC for high-speed/low-power applications

Abstract

449-71 1 San #24 NongseeRi Kiheung-eup Yongin-city KyunggIDo Korea SAMSUNG ELECTRONICS, SYSTEM LSI , SOC DEVELOPMENT TEAM " 4 c rWe propose a Reed-Solomon CODEC architecture. Chip was fabricated using 0 . 3 5~ technology. Since it was implemented as a programmable CODEC which can correct upto 16 errod32 erasures at once, it has versatility regardless of the number of correctable errors and the length of codeword for various applications. Suggested RS-CODEC has "True Block Pipelined Architecture" in which frame latency is equal to the length of codeword leading to maximize throughput to achieve highspeed and low-power at the same time. The input data rate can be amounted to 1 OOMByte per sec. 0-7803-6741-3/90 1/$10.00 0 2001 IEEE