No abstract

We propose a pipelined division architecture for low-power ECC applications, which is based on partialdivision on group basis and lookahead technique exploiting the linearity in finite field arithmetic. The throughput is one division per clock regardless of the degree of the dividend polynomial. The salient feature of this architecture is that it leads very low power-delay product. To verify the relative performance of the proposed division architecture over the conventional one using LFSR, three RS and BCH code applications were fabricated using 0.8µm double metal CMOS technology. Experimental results show about 32, 65, 67 times improvement in power consumption compared with conventional one using LFSR.

449-71 1 San #24 NongseeRi Kiheung-eup Yongin-city KyunggIDo Korea SAMSUNG ELECTRONICS, SYSTEM LSI , SOC DEVELOPMENT TEAM " 4 c rWe propose a Reed-Solomon CODEC architecture. Chip was fabricated using 0 . 3 5~ technology. Since it was implemented as a programmable CODEC which can correct upto 16 errod32 erasures at once, it has versatility regardless of the number of correctable errors and the length of codeword for various applications. Suggested RS-CODEC has "True Block Pipelined Architecture" in which frame latency is equal to the length of codeword leading to maximize throughput to achieve highspeed and low-power at the same time. The input data rate can be amounted to 1 OOMByte per sec. 0-7803-6741-3/90 1/$10.00 0 2001 IEEE