A Trust-Driven Placement Approach: A New Perspective on Design for Hardware Trust

Shekarian, Seyed Mohammad Hossein; Zamani, Morteza Saheb

doi:10.1142/s0218126615501157

Cited by 5 publications

(3 citation statements)

References 33 publications

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“…The addition of scan-chain features has little effect on the time complexity of the whole feature extraction algorithm. Therefore, there is no significant difference in time between our feature extraction algorithm and [20] and [21].…”

Section: Analysis Of Time Complexitymentioning

confidence: 99%

“…Formal verification method does not directly detect HT, but attempts to evaluate the reliability of IP core, and designs IP cores through trust strategies to improve the security of integrated circuits. In addition, the technology can isolate infected thirdparty IP through software scheduling protocol [20] or the correlation of input signals [21].…”

Section: A Formal Verifcationmentioning

confidence: 99%

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A Multi-Layer Hardware Trojan Protection Framework for IoT Chips

Dong

Liu

et al. 2019

IEEE Access

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Since integrated circuits are performed by several untrusted manufacturers, malicious circuits (hardware Trojans) can be implanted in any stage of the Internet-of-Things (IoT) devices. With the globalization of the IoT device manufacturing technologies, protecting the system-on-chip (SoC) security is always the keys issue for scientists and IC manufacturers. The existing SoC high-level synthesis approaches cannot guarantee both register-transfer-level and gate-level security, such as some formal verification and circuit characteristic analysis technologies. Based on the structural characteristics of hardware Trojans, we propose a multi-layer hardware Trojan protection framework for the Internet-of-Things perception layer called RG-Secure, which combines the third-party intellectual property trusted design strategy with the scan-chain netlist feature analysis technology. Especially at the gate level of chip design, our RG-Secure is equipped with a distributed, lightweight gradient lifting algorithm called lightGBM. The algorithm can quickly process high-dimensional circuit feature information and effectively improve the detection efficiency of hardware Trojans. In the meanwhile, a common evaluation index F-measure is used to prove the effectiveness of our method. The experiments show that RG-Secure framework can simultaneously detect register-transfer-level and gate-level hardware Trojans. For the trust-HUB benchmarks, the optimized lightGBM classifier achieves up to 100% true positive rate and 94% true negative rate; furthermore, it achieves 99.8% average F-measure and 99% accuracy, which shows a promising approach to ensure security during the design stage. INDEX TERMS Internet of Things, protection framework, hardware security, hardware Trojan.

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Section: Analysis Of Time Complexitymentioning

confidence: 99%

Section: A Formal Verifcationmentioning

confidence: 99%

A Multi-Layer Hardware Trojan Protection Framework for IoT Chips

Dong

Liu

et al. 2019

IEEE Access

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“…1). It is difficult to protect against such threats, but some solutions based on ad-hoc design and verification methods have been proposed [18], [19].…”

Section: Fig 1 Mains Threats To Ic Integritymentioning

confidence: 99%

On-chip Fingerprinting of IC Topology for Integrity Verification

Lecomte

Fournier

Maurine

2016

Proceedings of the 2016 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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The integrity of integrated circuits (ICs), in particular for detecting malicious add-ons like Hardware Trojans (HTs), have been studied in several recent research papers. The main limit of the proposed techniques so far is that the bias induced by the process variations restrict their efficiency and practicality. Most of those techniques compare two ICs' signatures while trying to get rid of the process variations. In this paper we propose a novel approach which in practice eliminates this limit. We first make the assumption that IC infection is done at a lot level, which is more realistic than models where infections are done on individual circuits. We introduce a variation model for the performance of CMOS structures in real designs which are different from test chips dedicated to the measure of process variations. This model is used to create signatures of lots which are independent of the process variations and is used as a base to define methods allowing to detect HTs and counterfeits in a straightforward way. The model and the methods are validated experimentally on 30 FPGA boards.

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An On-Chip Technique to Detect Hardware Trojans and Assist Counterfeit Identification

Lecomte¹,

Fournier²,

Maurine³

2017

IEEE Trans. VLSI Syst.

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International audienceThis paper introduces an embedded solution for the detection of hardware trojans (HTs) and counterfeits. The proposed method, which considers that HTs are necessarily inserted on production lots and not on a single device, is based on the fingerprinting of the static distribution of the supply voltage (V dd) over the whole surface of an integrated circuit. The measurement of this fingerprint is done through an array of sensors sensitive to the local V dd value and fingerprint extraction is based on a novel variation model of CMOS logic performance. This model takes into account not only process variations but also the impact of the design (layout, supply routing, and so on). In addition to the fingerprinting process, this paper introduces an adaptive distinguisher to deal with the difficult problem of fixing the p-value on large sets of statistical tests. The efficiency of the whole detection methodology is experimentally demonstrated on a set of 24 FPGA boards

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A Trust-Driven Placement Approach: A New Perspective on Design for Hardware Trust

Cited by 5 publications

References 33 publications

A Multi-Layer Hardware Trojan Protection Framework for IoT Chips

A Multi-Layer Hardware Trojan Protection Framework for IoT Chips

On-chip Fingerprinting of IC Topology for Integrity Verification

An On-Chip Technique to Detect Hardware Trojans and Assist Counterfeit Identification

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