No abstract

No abstract

During the last few years, hardware Trojan horses (HTHs) have become one of the most important threats to the security of very large scale integrated (VLSI) chips. Many e®orts have been made to facilitate the process of HTH detection, mostly based on the power analysis of chips. The techniques would be more bene¯cial if trust-driven techniques are used during the system design. Whereas design for hardware trust (DFHT) is one of the¯elds of interest, most current approaches include ad-hoc and gate-level design techniques. This paper discusses the advantage of physical-level design approaches with integrated strategies for improving the HTH-detection probability. As a proof of concept, a placement technique is presented with the goal of enhancing the ability of HTH detection techniques based on local power signal analysis. Our results show that the background e®ects on power pads can be leveraged by a simple partitioning-based placement algorithm. Minimizing the background e®ects leads to a better Trojan-to-background-e®ect ratio and more (by about 1.7 times) Trojan detectability.

No abstract