A Two-Dimensional Analysis Method on STI-Aware Layout-Dependent Stress Effect

Abstract

Strain technology has become indispensable for present CMOS integrated circuits (ICs) as the feature size of transistor shrinks. In the meantime, stress-induced variation has also become an unavoidable problem. Unintentional stress, such as shallow trench isolation (STI)-induced stress, is one of the main variation sources and is strongly layout dependent. In this paper, a new 2-D layout-dependent STI stress model and related device parameter model are proposed. The stress model captures layout parameters along both the longitudinal direction and the transverse direction, based on which channel stress induced by STI is derived. Device parameters including threshold voltage, mobility, and saturation velocity are then modified according to several analytical models. The model can be integrated into standard CMOS IC design flow. By comparing with TCAD simulation and experiments with 65-nm process, it shows that the new model can give a better prediction accuracy than the original process design kit.

The impact of shallow trench isolation effects on circuit performance

“…Furthermore, [3]- [6] use only a single component of the stress tensor for performance evaluation, while the entire stress tensor must be evaluated to accurately analyze STI-induced circuit performance variation. The work in [7] uses both longitudinal and transverse direction STI contributions, but is based on an empirically fitted model that is not scalable for nonrectangular shaped active/STI regions.…”

Shrinking Circuits Area with High-Mobility Channel MOSFETs

“…256kbit SRAM circuit areas of 65 nm technology were estimated assuming that only the peripheral circuit, which covers 60% of the total circuit area [14] , was shrunk and that cell areas are kept constant. Equal number of p-and nMOSFETs and an STI spacing of 290 nm [15] were also assumed. The chip area is estimated to be reduced to 77% by replacing Si n/pMOSFETs to In0.53Ga0.47As/Ge-channel MOSFETs under a condition of ∆VTH = 5 mV and Gm = 1 mS.…”

Analysis and Modeling of an 11.8 GHz Fin Resonant Body Transistor in a 14nm FinFET CMOS Process

“…2) V t Modulation Model: Stresses induced in the channel region cause changes to the band structure, which result in fluctuations in the band-edge potentials, band-gap, and the effective density of states [25]. Due to these shifts, the flatband voltage V F B and channel surface potential ψ s change, causing a change in the V t .…”

“…In this work, the model used in [34] is adapted for calculating the shift in conduction bandedge potential ∆E c due to time-varying strains in the channel. Changes to the valence band-edge potential ∆E v are evaluated using the model in [25]. Both conduction and valence bandedge potential shifts are evaluated as: while S x1x1 , S x2x2 and S x3x3 are time-varying, channelaveraged strain components, Ξ d , Ξ u , u 1 and u 2 are deformation potential constants (values given in Table III).…”