A two-dimensional subthreshold current model for strained-Si MOSFET

Abstract

An analytical model for the subthreshold current of a strained-Si metal-oxide-semiconductor field-effect transistor (MOSFET) is developed by solving the two-dimensional (2D) Poisson equation and the conventional drift-diffusion theory. Model verification is carried out using the 2D device simulator ISE. Good agreement is obtained between the model's calculations and the simulated results. By analyzing the model, the dependence of current on the strained-Si layer strain, doping concentration, source/drain junction depths and substrate voltage is studied. This subthreshold current model provides valuable information for strained-Si MOSFET design. strained-Si, MOSFET, surface voltage, subthreshold current PACS: 85.30.De, 85.30.TvSilicon devices play a decisive role in the semiconductor industry. Scaling down the feature size has been the main method of moving Si device's performance. However, as the device is scaled down to the nano scale, its performance approaches the physics limit. Strained-Si technology offers device designers the ability to enhance carrier mobility and modify the band gap, which is compatible with the existent Si device process. Recently, research about this strain engineering has been reported [1][2][3][4][5][6][7].Reports on the threshold voltage model of strained-Si metal-oxide-semiconductor field-effect transistor (MOSFET) can be found [3]. However, there has been no research done on this device regarding the subthreshold current, which is one of the main parts of power consumption in deep submicron integrated circuits. In this paper, a model for the subthreshold current of strained-Si MOSFET is developed by solving the two-dimensional (2D) Poisson equation in the stained-Si layer and the conventional drift-diffusion theory. By analyzing the model, the dependence of current on the strained-Si layer strain, doping concentration, source/drain junction depths and substrate voltage is studied. Model verification is carried out using the 2D device simulator ISE. Good agreement is obtained between the model's calculations and the simulated results.

The effect of substrate doping on the flatband and threshold voltages of a strained-Si pMOSFET

“…Such challenges have impelled researchers to look for various alternatives, and as a result, the strained-Si/SiGe (SSi/SiGe) material system has emerged. [1][2][3][4][5] By inducing strain into Si, the I-V characteristic of a strained-Si/SiGe p metal-oxide semiconductor field-effect transistor (pMOSFET) is enhanced, [6][7][8] but its C-V characteristic is distorted. A "plateau" has been observed in the gate C-V characteristics of a strained-Si/SiGe pMOSFET, and it can shift from the inversion region to the accumulation region as doping concentration increases, as shown in Fig.…”