A two-dimensional threshold voltage analytical model for metal-gate/high-k/SiO₂/Si stacked MOSFETs

Abstract

In this paper the influences of the metal-gate and high-k/SiO2/Si stacked structure on the metal—oxide—semiconductor field-effect transistor (MOSFET) are investigated. The flat-band voltage is revised by considering the influences of stacked structure and metal—semiconductor work function fluctuation. The two-dimensional Poisson's equation of potential distribution is presented. A threshold voltage analytical model for metal-gate/high-k/SiO2/Si stacked MOSFETs is developed by solving these Poisson's equations using the boundary conditions. The model is verified by a two-dimensional device simulator, which provides the basic design guidance for metal-gate/high-k/SiO2/Si stacked MOSFETs.