A two-in-one process for reliable graphene transistors processed with photo-lithography

Abstract

Research on graphene field-effect transistors (GFETs) has mainly relied on devices fabricated using electron-beam lithography for pattern generation, a method that has known problems with polymer contaminants. GFETs fabricated via photo-lithography suffer even worse from other chemical contaminations, which may lead to strong unintentional doping of the graphene. In this letter, we report on a scalable fabrication process for reliable GFETs based on ordinary photo-lithography by eliminating the aforementioned issues. The key to making this GFET processing compatible with silicon technology lies in a two-in-one process where a gate dielectric is deposited by means of atomic layer deposition. During this deposition step, contaminants, likely unintentionally introduced during the graphene transfer and patterning, are effectively removed. The resulting GFETs exhibit current-voltage characteristics representative to that of intrinsic non-doped graphene. Fundamental aspects pertaining to the surface engineering employed in this work are investigated in the light of chemical analysis in combination with electrical characterization.

Interface-Dependent Effective Mobility in Graphene Field-Effect Transistors

“…This means that a linear change of the top-gate potential is expected to result in a linear shift of V Dirac , proportional to the dielectric thickness. 8 However, as the top-gate potential decreases in these G-FETs, the effect it has on the transfer curve diminishes measurably. The shift of the Dirac voltage becomes smaller for each linear step of the top gate.…”

“…8 Graphene is inherently hydrophobic, 9 and the ALD process, which combines water and trimethylaluminum (TMA), can be problematic to implement. It is also known that, even though graphene is hydrophobic, it is thin enough that it can, to a certain extent, borrow the wettability of the surface below it.…”

“…With graphene in place on the wafer, 80-nm Au film was evaporated and test structures manufactured in accordance with our previously reported method. 8 The top dielectric was Al 2 O 3 , deposited by means of ALD, combined with a 1-nm Al seed layer, to thickness of 56 nm (600 cycles) to avoid pinholes and top-gate leakage. The ALD feed gases were TMA and water.…”

Laser Patterning a Graphene Layer on a Ceramic Substrate for Sensor Applications

“…Various graphene patterning techniques have been developed. Because of the fine 2D structure of graphene, the photolithography process has been applied successfully to the graphene Hall device [18], a graphene anode for an organic light-emitting diode (OLED) [19], interdigitated electrodes for planar micro-supercapacitors [20], and graphene field-effect transistors [21]. However, producing structures using photolithography requires masking and risks chemical contamination, which can cause unintentional doping of the graphene.…”

Microscale‐Patterned Graphene Electrodes for Organic Light‐Emitting Devices by a Simple Patterning Strategy

“…Besides that, complicated and time consuming transfer processes afterward is needed to transfer the patterned graphene to the desired substrate by using a supporting layer for its further application . Conventional photolithography combined with plasma etching is another method for microscale patterning of the CVD‐grown graphene . In this case, the transfer process is needed before the lithography patterning.…”