In this paper a new parallellserial convolver scheme with wavepipelining is proposed first. The design of the wavepipelined (WP) convolver using FPGAs is considered next. Convolvers with and without wavepipelining are implemented using Xilinx XC4006E FPGAs for convolving two sequences each with 8 bit accuracy and sequence length 8. The convolver without wavepipelining requires 125 CLBs and permits a minimum sampling period of 176 nsec. The WP convolver requires 217 CLBs and permits a minimum sampling period of 92 nsec. Further the multipliers in the WP convolver donot require the latches and an ASIC for a large WP convolver can result in significant savings in area and power. Finally three schemes for increasing the sampling rate of the WP convolver are suggested.
KeywordsConvolver, FPGA, wavepipelining
I Introduction:Convolvers also referred to as FIR filters are used in a no. of applications like MODEMS, Image processing, Control systems and Radar. Digital filters can be implemented either using programmable DSPs or using ASlCs and FPGAs. However, the implementation of digital convolvers using programmable DSPs is generally complex and costly for inputs sampled at 20 Mega samples per sec. (MSPS) and above. For these applications, FPGA based implementation is proposed as a cost effective solution .[I]. In this paper, it is shown how the performance of the FPGA based system can be enhanced further using wavepipelining.Wave pipelining is a design technique for increasing the throughput of a digital system without introducing pipelining registers between adjacent combinational logic blocks . Eventhough there are several papers describing the wavepipelining technique and its applications in ASlCs [2], [3], the application of wavepipelining 0-7803-6355-8/00/$10.0002000 IEEE technique for systems with sequential circuits has not been considered so far. This paper addresses this application by considering the implementation of an 1 D convolver using FPGA .The organisation of the paper is as follows:Section II discusses the. salient features of the serial/parallel convolver. Section II I discusses the methodology adopted for wavepipelining the convolver. Section IV presents the technique adopted for the design of the WP convolver using FPGAs. Section V gives the implementation details for a convolver used for convolving two sequence with 8 bit accuracy and sequence length 8. Section VI discusses three methods for improving the speed of the WP convolver,. Section VI1 gives a summary of the conclusions drawn.
II The serial/parallel convolverThe convolver computes the convolution of two sequences x = [ xo, , hN-, ] with M, N elements resulting in the sequence y with M+N-1 elements whose mth element is given by ,x,,,-, ] and h = [ ho, N-1 Ym = C hnxm-n n=OFor the application of the wavepipelining technique, the 1 D serial parallel convolver [3] shown in Fig.1 is chosen. This employs pipelining both at the word level and at the bit level. The multipliers in this circuit are implemented using seriaI/parallel multiplier shown ...
