A unified accelerator design for LiDAR SLAM algorithms for low-end FPGAs

Sugiura, Keisuke; Matsutani, Hiroki

doi:10.1109/icfpt52863.2021.9609886

Cited by 4 publications

(1 citation statement)

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“…This paper extends our previous work [51] by proposing a robustified version of the Hector SLAM [35], making our accelerator platform ROS-compliant, and integrating the accelerator into ROS-based Hector SLAM implementation. The previous work only considered the acceleration of particle filter-and graph-based SLAM, and overlooked scan matching-based SLAM, which is another important category.…”

Section: Related Workmentioning

confidence: 60%

A Universal LiDAR SLAM Accelerator System on Low-Cost FPGA

Sugiura

Matsutani

2022

IEEE Access

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LiDAR (Light Detection and Ranging) SLAM (Simultaneous Localization and Mapping) serves as a basis for indoor cleaning, navigation, and many other useful applications in both industry and household. From a series of LiDAR scans, it constructs an accurate, globally consistent model of the environment and estimates a robot position inside it. SLAM is inherently computationally intensive; it is a challenging problem to realize a fast and reliable SLAM system on mobile robots with a limited processing capability. To overcome such hurdles, in this paper, we propose a universal, low-power, and resource-efficient accelerator design for 2D LiDAR SLAM targeting resource-limited FPGAs. As scan matching is at the heart of SLAM, the proposed accelerator consists of dedicated scan matching cores on the programmable logic part, and provides software interfaces to facilitate the use. Our accelerator can be integrated to various SLAM methods including the ROS (Robot Operating System)-based ones, and users can switch to a different method without modifying and re-synthesizing the logic part. We integrate the accelerator into three widelyused methods, i.e., scan matching, particle filter, and graph-based SLAM. We evaluate the design in terms of resource utilization, speed, and quality of output results using real-world datasets. Experiment results on a Pynq-Z2 board demonstrate that our design accelerates scan matching and loop-closure detection tasks by up to 14.84x and 18.92x, yielding 4.67x, 4.00x, and 4.06x overall performance improvement in the above methods, respectively. Our design enables the real-time performance while consuming only 2.4W and maintaining accuracy, which is comparable to the software counterparts and even the state-of-the-art methods.INDEX TERMS SLAM, scan matching, FPGA.

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Section: Related Workmentioning

confidence: 60%