A unified approach for SoC testing using test data compression and TAM optimization

Iyengar, V.; Chandra, A.; Schweizer, S.; Chakrabarty, Krishnendu

doi:10.1109/date.2003.1253794

Cited by 18 publications

(15 citation statements)

References 4 publications

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“…Many techniques have been proposed for TAM/wrapper design under different constraints (e.g., testing time, test bus width, power dissipation, control overhead, routing, and layout) [8]- [16]. However, these techniques either do not consider test data compression, or they utilize relatively inefficient compression techniques [17].…”

mentioning

confidence: 99%

Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip

Wang

Chakrabarty

Wang³

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-We present a system-on-chip (SOC) testing approach that integrates test data compression, test-access mechanism/test wrapper design, and test scheduling. An efficient linear feedback shift register (LFSR) reseeding technique is used as the compression engine. All cores on the SOC share a single on-chip LFSR. At any clock cycle, one or more cores can simultaneously receive data from the LFSR. Seeds for the LFSR are computed from the care bits for the test cubes for multiple cores. We also propose a scan-slice-based scheduling algorithm that attempts to maximize the number of care bits the LFSR can produce at each clock cycle, such that the overall test application time (TAT) is minimized. This scheduling method is static in nature because it requires predetermined test cubes. We also present a dynamic scheduling method that performs test compression during test generation. Experimental results for International Symposium on Circuits and Systems and International Workshop on Logic and Synthesis benchmark circuits, as well as industrial circuits, show that optimum TAT, which is determined by the largest core, can often be achieved by the static method. If structural information is available for the cores, the dynamic method is more flexible, particularly since the performance of the static compression method depends on the nature of the predetermined test cubes.

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mentioning

confidence: 99%

Integrated LFSR Reseeding, Test-Access Optimization, and Test Scheduling for Core-Based System-on-Chip

Wang

Chakrabarty

Wang³

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Self Cite

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“…In this case however, the distribution mechanism can be a simple buffer [16], when the internal TAM and the external TAM are the same, or a time multiplexing scheme [9]. As noted in [16] the decoder and control overhead of this scheme is reduced in comparison with scenario (a), at the expense of increased test time. While avoided in the figure for clarity the number of decoder's outputs which drive the groups of cores may not be equal among all groups.…”

Section: Analysis Of Tdc-tam Interactionmentioning

confidence: 99%

“…In this section we provide an analysis of previous work which focuses on integrated TDC-TAM test solutions [5,9,10,16], considering a control and area-overhead perspective. Previous work analysis for TDC and TAM design are detailed in [12,17] and [8], respectively.…”

Section: Analysis Of Tdc-tam Interactionmentioning

confidence: 99%

“…The approaches analyzed above [5,9,10,16] use TDC methods which are either single-scan chain based [5,10,16] or are not sensitive to the test bus width [9]. Therefore, these compression methods can be added on-top of existing TAM design solutions without any changes to the design flow, and with small performance degradation, in terms of test time and test data, of the compression method.…”

Section: Analysis Of Tdc-tam Interactionmentioning

confidence: 99%

“…This mechanism can be an interleaving architecture as illustrated in [5], a distributed architecture as proposed in [10], or a time multiplexing scheme [16]. In all the cases [5,10,16] the distribution mechanism has the external TAM of width much smaller than the internal TAM; for example 1 : n (for n cores) in [5,10]. However, since each core is provided with a decoder, for a large number of cores the area and control overhead is considerable.…”

Section: Analysis Of Tdc-tam Interactionmentioning

confidence: 99%

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