A unified approach for trap-aware device/circuit co-design in nanoscale CMOS technology

Wang, Runsheng; Luo, Mulong; Guo, Shaofeng; Huang, Ru; Liu, Changze; Zou, Jibin; Wang, Jianping; Wu, Jingang; Xu, Nuo; Wong, Waisum; Yu, Scott; Wu, Hanming; Lee, Shiuh-Wuu; Wang, Yangyuan

doi:10.1109/iedm.2013.6724745

Cited by 28 publications

(7 citation statements)

References 3 publications

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“…In the device domain, recent studies have demonstrated that BTI and RTN, along with the random trap fluctuation (RTF), are consistently correlated with the physical trapping/detrapping effects of gate oxide traps as shown in Figure 13(b) [117]. In the nanometer scale, NBTI effects have shifted from deterministic degradations to stochastic ones due to limited number of gate oxide traps within each device [132][133][134][135].…”

Section: Design For Reliability (Dfr)mentioning

confidence: 99%

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Design for manufacturability and reliability in extreme-scaling VLSI

Roy

et al. 2016

Sci. China Inf. Sci.

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In the last five decades, the number of transistors on a chip has increased exponentially in accordance with the Moore's law, and the semiconductor industry has followed this law as long-term planning and targeting for research and development. However, as the transistor feature size is further shrunk to sub-14nm nanometer regime, modern integrated circuit (IC) designs are challenged by exacerbated manufacturability and reliability issues. To overcome these grand challenges, full-chip modeling and physical design tools are imperative to achieve high manufacturability and reliability. In this paper, we will discuss some key process technology and VLSI design co-optimization issues in nanometer VLSI.

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Section: Design For Reliability (Dfr)mentioning

confidence: 99%

“…Examples of lithography hotspots[112]. Color online) (a) Stacking effect in NOR gate; (b) various reliability/variability issues induced by gate oxide traps[117].…”

mentioning

confidence: 99%

Design for manufacturability and reliability in extreme-scaling VLSI

Roy

et al. 2016

Sci. China Inf. Sci.

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“…Based on our newly proposed method [17], the approach for accurate simulation of RTN effects in digital circuits is shown in Fig. 6.…”

Section: A Ac Rtn Vs DC Rtn: Silicon Evidence and Modelingmentioning

confidence: 99%

Impact of temporal transistor variations on circuit reliability

Wang

Cao

2015

2015 IEEE International Symposium on Circuits and Systems (ISCAS)

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With the ever-increasing importance of temporal transistor variations during circuit run time and aging, this paper focuses on impacts of the two major temporal effects: the Bias Temperature Instability (BTI) and Random Telegraph Noise (RTN), illustrating their scaling trend, challenges, and potential solutions for future design robustness. Keywords-circuit reliability; temporal variation; bias temperature instability (BTI); random telegraph noise (RTN)I.

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“…In particular, bias temperature instability (BTI) stresses reduce the read margin of the SRAM cell and affect its stability, leading to possible read fails [6]. So far this concern has been investigated either by simulations or by conventional measurements [7]- [9] of the read static noise margin (RSNM) degradation using the well-known butterflycurve technique [10]. However, using this slow two-steps technique leads to inaccurate characterization of the dynamic variability in SRAM cells.…”

Section: Introductionmentioning

confidence: 97%

A Complete Characterization and Modeling of the BTI-Induced Dynamic Variability of SRAM Arrays in 28-nm FD-SOI Technology

Husseini

Garros

Cluzel

et al. 2014

IEEE Trans. Electron Devices

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In this paper, we present for the first time a direct measurement procedure to characterize the bias temperature instability (BTI)-induced dynamic variability in static random access memory (SRAM) cells. This measurement procedure is based on the supply read retention voltage metric. The variability results obtained with this technique are explained by means of Monte Carlo SPICE simulations. The analytical model is then proposed to extrapolate this BTI-induced variability at different stress conditions. Finally, the impact of this variability on a large SRAM array is investigated. A semianalytical method is first developed to calculate the fresh read failure probability for different operating voltages V DD . The model is then extended to address the effect of BTI stress on the SRAM array. Results show that under SRAM cells operating conditions the bitcell read stability is barely impacted by BTI stress even after 10 years of work.Index Terms-Bias temperature instability (BTI) stress measurements, BTI stress modeling, read failure probability evaluation, static random access memory (SRAM) cells, supply read retention voltage (SRRV) metric.

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A unified approach for trap-aware device/circuit co-design in nanoscale CMOS technology

Cited by 28 publications

References 3 publications

Design for manufacturability and reliability in extreme-scaling VLSI

Design for manufacturability and reliability in extreme-scaling VLSI

Impact of temporal transistor variations on circuit reliability

A Complete Characterization and Modeling of the BTI-Induced Dynamic Variability of SRAM Arrays in 28-nm FD-SOI Technology

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