A unified approach to partitioning and placement (VLSI layout)

Tsay, Ren-Song; Kuh, E.S.

doi:10.1109/31.76488

Cited by 52 publications

(35 citation statements)

References 11 publications

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“…It is easy to express it as an integer linear program [22]. Without loss of generality, consider the case of splitting the set into two partitions and of equal size.…”

Section: B Partitioning the Problemmentioning

confidence: 99%

Scalable Offline Optimization of Industrial Wireless Sensor Networks

Palopoli

Rizano

2011

IEEE Trans. Ind. Inf.

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Abstract-Sensor networks are increasingly used to control and monitor industrial and manufacturing processes. In this paper, we consider the problem of optimizing a cost function for wireless sensor networks of this kind under energy consumption constraints. We focus, in particular, on the problem of coverage optimization through scheduling. Following existing approaches, we use a mixed integer linear program formulation. We show how to use partitioning techniques to decompose the problem into separate subproblems, solved individually, overcoming the exponential complexity typical of integer linear programming, while minimizing the loss in optimality. In addition, we evaluate the achieved degree of optimality by computing relatively tight bounds with respect to the optimal solution. Finally, we employ simple but effective heuristics to further improve our solution. The results show that our procedure is very efficient and scalable, and is able to find solutions that are very close to optimal. These characteristics make our approach a perfect fit for large and fixed deployments of wireless sensors, typical in factory automation and industrial applications. To show the generality of the approach, we apply our methodology to three different models of varying complexity.

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“…It is easy to express it as an integer linear program [22]. Without loss of generality, consider the case of splitting the set into two partitions and of equal size.…”

Section: B Partitioning the Problemmentioning

confidence: 99%

Scalable Offline Optimization of Industrial Wireless Sensor Networks

Palopoli

Rizano

2011

IEEE Trans. Ind. Inf.

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“…This has resulted in a focus in the literature on techniques for spreading the cells. Commonly this is done iteratively, either through the addition of "spreading forces" or extra fixed points [EJ98,HMS02,VC04] or using graph partitioning techniques to subdivide the die into disjoint areas and force spreading by assigning cells to these areas [TKH88,TK91a,KSJ88].…”

Section: Placementmentioning

confidence: 99%

“…At the topmost levels, where the partitioning is coarse and the information from the QP solution is less useful to guide the partitioning, we use hMetis [KAKS97,KK99] to partition the hypergraph without regard to geometry. For finer divisions, we choose a cut-minimizing spectral partition based on the QP solution, similar to the techniques described in [TKH88,TK91a].…”

Section: Placement Driven By Sequential Timingmentioning

confidence: 99%

Integration of Physical Design and Sequential Optimization

Chong¹

2006

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Public reporting burden for the collection of information is estimated to average 1 hour per response, including the time for reviewing instructions, searching existing data sources, gathering and maintaining the data needed, and completing and reviewing the collection of information. Send comments regarding this burden estimate or any other aspect of this collection of information, including suggestions for reducing this burden, to Washington Headquarters Services, Directorate for Information Operations and Reports, 1215 Jefferson Davis Highway, Suite 1204, Arlington VA 22202-4302. Respondents should be aware that notwithstanding any other provision of law, no person shall be subject to a penalty for failing to comply with a collection of information if it does not display a currently valid OMB control number. This work examines the interaction between the physical design of digital integrated circuits and sequential optimization techniques used for performance enhancement. In particular, the integration of floorplanning and placement with retiming and clock skew scheduling is explored. A theoretical result is given which addresses the computational complexity of circuit partitioning under constraints derived from sequential optimization; this motivates the need for heuristic approaches to the related placement problem. Another theoretical result provides a characterization of the feasible retimings of a sequential circuit; this result is used to motivate an effective method for floorplanning integrated with sequential optimization. Practical techniques for using sequential slack to drive standard-cell placement are shown here; experiments demonstrate significant improvement in final design performance using these methods. Another part of this work examines how the role of sequential optimization and physical design changes when the design allows for asynchronous or latency-insensitive communication between modules. A theoretical result relating to the problem of clock tree implementation for clock skew scheduling under process variation is given. Finally an experimental technique for floorplanning using nonlinear programming is demonstrated. All rights reserved.Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission. Integration of Physical Design and Sequential

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“…As instance sizes grow larger, movebased (e.g., annealing) methods may be too slow except for detailed placement improvement. Due to its speed and "global" perspective, the so-called quadratic placement technique has received a great deal of attention throughout its development by such authors as Wipfler et al [16], Fukunaga et al [9], Cheng and Kuh [6], Tsay and Kuh [15] and others. Indeed, quadratic placement is reputedly an approach that has been used within commercial tools for placement of standard-cell and gate-array designs.…”

Section: Introductionmentioning

confidence: 99%

Quadratic Placement Revisited

Alpert¹,

Chan²,

Huang³

et al.

Proceedings of the 34th Design Automation Conference

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The "quadratic placement" methodology is rooted in [6] [14] [16] and is reputedly used in many commercial and in-house tools for placement of standard-cell and gate-array designs. The methodology iterates between two basic steps: solving sparse systems of linear equations, and repartitioning. This work dissects the implementation and motivations for quadratic placement. We first show that (i) Krylov subspace engines for solving sparse systems of linear equations are more effective than the traditional successive over-relaxation (SOR) engine [15] and (ii) order convergence criteria can maintain solution quality while using substantially fewer solver iterations. We then discuss the motivations and relevance of the quadratic placement approach, in the context of past and future algorithmic technology, performance requirements, and design methodology. We provide evidence that the use of numerical linear systems solvers with quadratic wirelength objective may be due to the pre-1990's weakness of min-cut partitioners, i.e., numerical engines were needed to provide helpful hints to min-cut partitioners. Finally, we note emerging methodology drivers in deep-submicron design that may require new placement approaches to the placement problem.

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A unified approach to partitioning and placement (VLSI layout)

Cited by 52 publications

References 11 publications

Scalable Offline Optimization of Industrial Wireless Sensor Networks

Scalable Offline Optimization of Industrial Wireless Sensor Networks

Integration of Physical Design and Sequential Optimization

Quadratic Placement Revisited

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