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We propose an efficient circuit placement approach based on analytic net weighting controls for nonlinear performance constraints. We justify the popular net weighting heuristic by first showing that an appropriate net weighting is a natural result of the Kuhn-Tucker conditions of circuit placement optimization subject to the performance constraints. We further give a quantitative analysis of the effect of net weighting to wire length change. An effective net weighting control algorithm has been implemented and applied to real chip designs. The results are very promising. A performance-optimized result can be achieved in 13.2 seconds for a chip with 1,403 circuits. An experimental CMOS chip with 45,296 circuits has a complete placement result in 40 minutes while the wire length measure is 20.3 percent better than a simulated annealing approach.