A Unified PUF and TRNG Design Based on 40-nm RRAM With High Entropy and Robustness for IoT Security

Gao, Bin; Lin, Bohan; Li, Xueqi; Tang, Jianshi; Qian, He; Wu, Huaqiang

doi:10.1109/ted.2021.3138365

Cited by 40 publications

(19 citation statements)

References 28 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In most PUF demonstrations, the BER is well above this allowed range, thus requiring the addition of the invariably dominant area and energy cost of ECC (e.g., 2-3 orders of magnitude higher than the raw PUF and post-processing). In a few silicon demonstrations, the native BER has reached sufficiently low levels that allow the suppression of ECC in embedded DRAM PUFs [19], oxide rupture-based PUFs [45], and RRAM arrays in view of their pronounced process variations [46]. As in Fig.…”

Section: A Trends and Advances In Physically Unclonable Functionsmentioning

confidence: 99%

“…As in Fig. 3c, innovation in post-processing techniques is substantially improving the stability in most PUF architectures, especially in non-volatile memory-based [46]- [50] and analog PUFs [24]- [27]. Volatile memory-based PUFs are also substantially improving [17]- [23], and allow ECC-less operation through methods such as VSS-bias generator for dark bit detection [20] and hot carrier injection-induced stability reinforcement [21].…”

Section: A Trends and Advances In Physically Unclonable Functionsmentioning

confidence: 99%

“…However, their energy efficiency is still competitive and near to best-in-class. Noise-based TRNGs lie in the higher end of the area and energy range [46], [78]- [81]. Best-in-class energy efficiency is achieved by specific demonstrations belonging to the jitter-based [63], chaotic map [69], [70] and metastability-based TRNGs [55], [56].…”

Section: B Trends and Advances In True Random Number Generatorsmentioning

confidence: 99%

“…An in-memory TRNG was also shown in a voltage-controlled MRAM array [82], which eliminates the need for calibration in TRNG mode. A unified PUF+TRNG has been also demonstrated in an RRAM array [46], which enables design reuse in an inherently high-density fabric.…”

Section: A In-memory Primitivesmentioning

confidence: 99%

See 3 more Smart Citations

Aggressive Design Reuse for Ubiquitous Zero-Trust Edge Security—From Physical Design to Machine-Learning-Based Hardware Patching

Alioto

2023

IEEE Open J. Solid-State Circuits Soc.

View full text Add to dashboard Cite

This work presents an overview of challenges and solid pathways towards ubiquitous and sustainable hardware security in next-generation silicon chips at the edge of distributed and connected systems (e.g., IoT, AIoT). As first challenge, the increasingly connected nature and the exponential proliferation of edge devices is unabatingly increasing the overall attack surface, making attacks easier and mandating ubiquitous security down to each edge node. At the same time, the necessity to incorporate zero-trust policies in large-scale distributed systems requires a complete set of security primitives for hardware-backed authentication, and a higher degree of physical context awareness (including primitives detecting the onset of physical attacks). Thus, making the inclusion of such security primitives economically sustainable even in low-end devices is a second key challenge. As third challenge, the ever-changing vulnerability landscape and the need for increased chip longevity in distributed systems requires security assurance methods that are sustainable and adaptive across the entire chip lifecycle. In this work, design principles and promising directions to enable ubiquitous and sustainable security capabilities along with physical awareness are discussed. Such achievements require a fundamental rethinking of design methodologies to enable aggressive design and resource reuse (e.g., area, power, design effort), along with low-cost on-chip sensorization and intelligence for physical attack detection. Such rethinking inevitably crosses over the traditional design abstractions, and requires innovation from the physical to the algorithmic level. At the physical and circuit level, design and resource reuse is enabled by immersed-inlogic and in-memory security approaches. At the algorithm level, "hardware patching" is introduced and exemplified to show that run-time intelligence (machine learning) allows security capabilities to adapt and improve over time, as typical of security patching in software. Sensing techniques to detect attacks in situ from non-invasive to invasive are illustrated, while still preserving fully-automated design approaches. Overall, the above design principles are expected to push security capabilities in distributed systems to a new level, ultimately making the edge more intelligent and self-reliant, and security measures more distributed.

show abstract

Section: A Trends and Advances In Physically Unclonable Functionsmentioning

confidence: 99%

Section: A Trends and Advances In Physically Unclonable Functionsmentioning

confidence: 99%

Section: B Trends and Advances In True Random Number Generatorsmentioning

confidence: 99%

Section: A In-memory Primitivesmentioning

confidence: 99%

See 2 more Smart Citations

Aggressive Design Reuse for Ubiquitous Zero-Trust Edge Security—From Physical Design to Machine-Learning-Based Hardware Patching

Alioto

2023

IEEE Open J. Solid-State Circuits Soc.

View full text Add to dashboard Cite

show abstract

“…However, the new approaches unified the TRNG with the memories used in the system, reducing the area overhead. The unified TRNG uses the different physical phenomena to generate random sequence with the undesirable effects in the Static memory (SRAM) [31], [32], Dynamic memory (DRAM) [33], [34], Resistive memory (RRAM) [35]- [38], Magnetic memory (MRAM) [39], [40]. An NVRAM with the control gate methodology can be used for TRNG applications, reading the noise while sensing their threshold voltage [10].…”

Section: Introductionmentioning

confidence: 99%

A Unified NVRAM and TRNG in Standard CMOS Technology

et al. 2022

View full text Add to dashboard Cite

show abstract

Atomic Layer Deposition Films for Resistive Random‐Access Memories

Hao,

Peng,

Zierold

et al. 2024

Adv Materials Technologies

View full text Add to dashboard Cite

Resistive random‐access memory (RRAM) stands out as a promising memory technology due to its ease of operation, high speed, affordability, exceptional stability, and potential to enable smaller memory devices with sizes under 10 nm. This has drawn significant attention, with atomic layer deposition (ALD) emerging as an ideal technology to tackle the challenges of nanoscale fabrication in the micro‐ and nanomanufacturing industry. ALD offers technological advantages such as functional multiple‐layer stacking, doping capabilities, and incorporating oxygen reservoirs or reactive layers. These factors contribute to achieving more intriguing, stable, and reliable nonvolatile resistance switching behaviors in RRAM. Specifically, ALD greatly benefits RRAM, that relies on the valence change mechanism, where high‐k transition metal oxides are commonly used as switching materials, and precise control over oxygen vacancies is achievable. This review provides a comprehensive overview of ALD films used in RRAM, delves into resistive switching properties and microscopic mechanisms in binary and ternary oxides and nitrides, and explores the impact of ALD‐prepared electrodes. Furthermore, the current status and future prospects of ALD‐based RRAM are highlighted, which is poised to catalyze further advancements in the fields of information storage and neural networks.

show abstract

A Unified PUF and TRNG Design Based on 40-nm RRAM With High Entropy and Robustness for IoT Security

Cited by 40 publications

References 28 publications

Aggressive Design Reuse for Ubiquitous Zero-Trust Edge Security—From Physical Design to Machine-Learning-Based Hardware Patching

Aggressive Design Reuse for Ubiquitous Zero-Trust Edge Security—From Physical Design to Machine-Learning-Based Hardware Patching

A Unified NVRAM and TRNG in Standard CMOS Technology

Atomic Layer Deposition Films for Resistive Random‐Access Memories

Contact Info

Product

Resources

About