A unified transformational approach for reductions in fault vulnerability, power, and crosstalk noise & delay on processor buses

Abstract

In this paper we propose a coding scheme for general-purpose applications that can reduce power dissipation, crosstalk noise and crosstalk delay on the bus lines while simultaneously detecting errors at run time. The reduction in power dissipation can be achieved through reducing the bus switching activity. Not only is the switching activity in individual lines reduced but so is the coupling activity across the adjacent lines, the major contributor to the overall power dissipation in deep submicron technology. Detailed analysis of crosstalk noise and delay shows that eliminating certain patterns of transitions and reducing the infeasible ones in terms of crosstalk noise and power dissipation is a feasible strategy for alleviating these problems. We propose an encoding technique consisting of the use of predefined patterns of transitions, one for each possible combination of input data, to generate the codewords. The restriction to the predefined patterns of transitions enables fast encoding and low hardware overhead. This work presents an extensive analysis of the consequent reduction in crosstalk and power. SPICE derived experimental results show a reduction in worst case crosstalk delay and noise, ranging up to 24% and 10% respectively. Extensive experimental results for various applications show significant reduction in power dissipation ranging up to 44% for switching activity on the bus lines and up to 25% for coupling activity. The results also show a drastic reduction ranging up to 98% in the number of patterns that are most likely to produce crosstalk errors.

Reliable network-on-chip design for multi-core system-on-chip

“…In the case of two lines, the crosstalk delay worst cases occur when the signal on adjacent lines switches in opposite directions. From the experimental results in [2] we can find that the numbers of 2-bit adjacent transitions ( ), 2-aggressor transitions and 3-aggressor transitions are still large.…”

“…These codes addressed the power problem but did not address the delay problem. Crosstalk avoidance codes (CAC) that reduce the delay by forbidding specific transitions were recently proposed [2,11,12,17,21,23]. Though crosstalk between adjacent wires is addressed by CAC, other forms of DSM noise such as power grid fluctuations, crosstalk from other interconnects, electromagnetic interference make buses susceptible to errors.…”

“…Ayoub [2] proposed a coding scheme for general-purpose applications that can reduce power dissipation, crosstalk noise and crosstalk delay on the bus lines while simultaneously detecting errors at runtime. They used four data bits with one redundant bit for crosstalk avoidance coding, and it also used one additional shielding line every ten bits.…”

“…We summarize the possible transition patterns that are most likely to produce crosstalk delay and noise in Table 1. In the case of three lines, the crosstalk noise worst cases could occur either when the signal on the victim line is steady high and the signals on the aggressors (adjacent active lines) switch from high to low or when the signal on the victim line is steady low and the signals on the neighboring lines are switched from low to high [2]. The crosstalk delay worst cases could occur when the three lines switch simultaneously with the center line switching in a direction opposite to its neighbors, which maximizes the crosstalk delay as well.…”

“…In Sect. 6, we will show some experimental results compared with the design [2]. Figure 1 shows the generic communication system for data transmission over a noisy channel [20].…”