A unified VLSI algorithm for a high performance systolic array implementation of type IV DCT/DST

Abstract

An efficient design approach to derive a unified high performance systolic array architecture for prime length type IV DCT and DST is proposed. This approach is based on a unified VLSI algorithm that uses a parallel restructuring of type IV DCT and DST. It uses parallel pseudo-circular correlation structures as basic computational forms. Most of the unified algorithm can be implemented on the same hardware structure leading to a VLSI chip with a very high percentage of the chip area being used by both the transforms. The unified algorithm can be mapped onto a linear systolic array that have a small number of I/O channels and low I/O bandwidth, which can be efficiently implemented into a VLSI chip.I.

An Area-Efficient Unified VLSI Architecture for Type IV DCT/DST Having an Efficient Hardware Security with Low Overheads

“…When comparing to existing unified VLSI architectures for DCT/DST IV, we can see that, in [22], the throughput is significantly lower due to the fact that we have three shorter systolic arrays operating in parallel, in contrast with two longer systolic arrays in [22]. The hardware core in [22] has N general multipliers and N adders as compared with 3(N − 1)/4 multipliers, with a constant and 3(N − 1)/4 adders in the proposed solution. Moreover, the solution proposed in [22] does not incorporate the obfuscation technique.…”

“…The hardware core in [22] has N general multipliers and N adders as compared with 3(N − 1)/4 multipliers, with a constant and 3(N − 1)/4 adders in the proposed solution. Moreover, the solution proposed in [22] does not incorporate the obfuscation technique.…”

“…Also, it is not possible to obtain an efficient unified architecture and to include the obfuscation technique. Due to the fact that, in our solutions, the general multipliers have been replaced with multipliers with a constant, the hardware complexity of the implementation has been further reduced as compared with the VLSI implementation in [22,28] where a general multiplier with a significant greater hardware complexity and latency has been used. Since the delay on the critical path has been considerably reduced and we have applied a hardware sharing technique by means of interleaving, we have succeeded in maintaining a low hardware complexity and achieved high-speed performance.…”

“…There are very many good VLSI implementations for type II and type III DCT, and quite a few good hardware implementations for type IV DCT or type IV DST [20][21][22][23][24][25][26][27][28][29]. Among them, there are only a few unified solutions that can efficiently execute both transforms using a large portion of the area in common on the same chip [20][21][22]28].…”

A New Approach for a Unified Architecture for Type IV DCT/DST with an Efficient Incorporation of Obfuscation Technique

“…In [32][33][34][35][36][37][38][39], we see a hardware accelerator for the computation of DCT-IV. In the proposed method, each data from the input sequence is fed to a multiplier and to an accumulator.…”