A Unique Design of Hybrid Full Adder for the Application of Low Power VLSI Circuits

Singh, Salam Surjit; Leishangthem, Dolly; Shah, Md. Nasiruddin; Shougaijam, Biraj

doi:10.1109/iceca49313.2020.9297594

Cited by 11 publications

(6 citation statements)

References 13 publications

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“…In the present study, using Pass Transistor Logic (PDL), CMOS transfer gate and single Hybrid Full Adder (HFA) logic in 90 Nm technology was developed [7]. Because the transistor produces a CMOS that accepts various constants, it is the fundamental role of consumption power.…”

Section: Literature Surveymentioning

confidence: 99%

RETRACTED ARTICLE: A Novel Adaptive Current Control Technique Based Modified MOS Current Mode Logic Circuits for Low Power and Area Efficient

Pradeep¹,

Rani²,

Kumar³

et al. 2021

Wireless Pers Commun

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MOS current mode logic (MCML) is one of the most promising logic functions to counteract power analysis attacks. The static power MCML standard cells are significantly higher than the static CMOS logic to achieve an equivalent function. As a result, using such logical patterns is very limited in portable devices. The strange thing is that these devices are the most sensitive to physical attacks, which will benefit more people from passing MCML. The propose to overcome this limitation by significantly reducing the static power consumption of MCML-based full adder circuits. For this reason, current control by adaptive (ACCT) -MCML standard cell library is provided in each transistor cell suspension. The effect of sleep transistors on performance and area is negligible. In addition, the proposed difference library is compatible with Micro wind tools. The integrated real-time digital signal processing application, where the drive current must be high. The conventional design will have a low-efficiency supply voltage with low capacitance; even when operating, the circuit speed will be faster, and the delay will be high. So the proposed 14 T full adder based integrated circuit and adder are based on ACCT, which High power consumption, which has become an essential standard operation for the design of energy-efficient dedicated circuits, has become the primary function and compact device design, possible output. The coefficient plays a significant role in planning energy-saving processors and determining processor performance. Especially, the switching behavior is to diminish the power consumption of the design MCML full ladder logic. However, the performance of the circuit is less than the full adder binary logic. The proposed circuit's correctness and effectiveness are verified by Micro wind with a proposed MCML process of 0.13 μm and a power supply voltage of 4.2 V.

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Section: Literature Surveymentioning

confidence: 99%

RETRACTED ARTICLE: A Novel Adaptive Current Control Technique Based Modified MOS Current Mode Logic Circuits for Low Power and Area Efficient

Pradeep¹,

Rani²,

Kumar³

et al. 2021

Wireless Pers Commun

View full text Add to dashboard Cite

show abstract

“…Despite CMOS' benefits, other methods are now being utilized as alternatives since CMOS requires a lot of space, has a lot of internal nodes, and generates a lot of static power because there are direct paths from the power supply (VDD) to the ground (GND). To reduce the power delay product (PDP) utilized in the fundamental VLSI circuit building blocks, full adders are created using pass transistor logic (PTL), CMOS logic, and an inverter logic next to XOR logic to create the logic of XNOR [5]. In order to eliminate circuit faults and arithmetic circuit errors, selfchecking and self-repairing capabilities are proposed and employed, primarily in industrial applications, to consume little power and operate at high speed [6].…”

Section: IImentioning

confidence: 99%

Design of Full Swing Carry Generator Using Mentor Graphics

Venkatachari¹,

Priyanka.²,

Adapala³

et al. 2023

IJRASET

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A Full adder is built specifically for creating full-swing carry output utilizing Mentor graphics in this project. Mentor Graphics is electronic design automation software that is used to create superior electronic devices more quickly and costeffectively. The proposed circuit, which has a high driving capability, is suitable for a wide range of multistage structure applications. In digital processing equipment, full adders are used for multiple adders. This circuit design employs a unique mode to provide a full swing carry output, and its performance is governed by suitable inputs, static power reduction, and transistor series construction. The full adder proposed here is an efficient gate for Integrated Circuits (ICs). The performance between simulation and measurement produced a very good approximation result. When compared to other circuits, the cell's performance under variations indicates its excellent driving capabilities while consuming very little power and PDP. The circuit makes use of a one-of-a-kind module to provide full-swing Carry output, and its performance is governed by appropriate inputs, static power reduction, and transistor series formations.

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“…In contrast to CMOS logic, pass-transistor logic, which consists of pass transistors or pass gates, has been of great interest due to its advantage in the number of transistors. Since [9] first proposed a PTL-based FA circuit in 1992, a variety of PTL-based full adders have been proposed [10][11][12][13].…”

Section: Introductionmentioning

confidence: 99%

“…Additionally, ref. [13] devised a hybrid FA architecture necessitating just 13 transistors, yet its application in more intricate circuit configurations remains unexplored.…”

Section: Introductionmentioning

confidence: 99%

Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model

Yu,

Pan,

Tang

et al. 2024

Electronics

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The multiplier is the fundamental component of many computing modules. As the most important component of a multiplier, the full adder (FA) also has a significant impact on the overall performance. Full adders based on pass transistor logic (PTL) have been a very popular research field in recent years, but the uneven delay makes it difficult to analyze the critical path of multipliers based on PTL full adders. In this paper, we propose a model to evaluate the critical path of the carry save array (CSA) multiplier that could reduce the size of the simulation input set from 4 G to 93 K to finally obtain the maximum delay of the multiplier. We propose a novel low-power, high-speed CSA multiplier based on both PTL full adders and CMOS full adders, using our critical-path evaluation model. The proposed work is implemented in the 28 nm process. We use the model to reduce the worst-case delay by 14.5%. The proposed multiplier improved the power delay product by 9.4% over the conventional full CMOS multiplier.

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A Unique Design of Hybrid Full Adder for the Application of Low Power VLSI Circuits

Cited by 11 publications

References 13 publications

RETRACTED ARTICLE: A Novel Adaptive Current Control Technique Based Modified MOS Current Mode Logic Circuits for Low Power and Area Efficient

RETRACTED ARTICLE: A Novel Adaptive Current Control Technique Based Modified MOS Current Mode Logic Circuits for Low Power and Area Efficient

Design of Full Swing Carry Generator Using Mentor Graphics

Design of a High-Speed, Low-Power PTL-CMOS Hybrid Multiplier Using Critical-Path Evaluation Model

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