A UWB receiver with modified CS‐CG LNTA: Noise and nonlinearity analysis

Javadi, Mohsen; Naimi, Hossein Miar; Andargoli, Seyed Mehdi Hosseini

doi:10.1002/cta.2621

Cited by 3 publications

(2 citation statements)

References 12 publications

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“…In [10,11], there are RAKE receivers consisting of multiple parallel correlators for complex multipath channel environments and transmission reference (TR) receivers [12][13][14][15], which do not require complex channel estimation compared to RAKE receivers. In [16][17][18][19][20][21], the structure of the low-noise ampli er (LAN) is optimized to improve the gain of the LAN and reduce the noise so as to improve the data speed of the receiver and reduce the bit error rate (BER). In [22][23][24][25], the algorithm of analog-to-digital converter (ADC) is optimized to reduce the bit error rate of the receiver.…”

Section: Introductionmentioning

confidence: 99%

Modeling and Simulation of Ultra-Wideband Communication Receiver Based on Balanced Sampling and Integrating Circuit

Wang

Huang

Hao

et al. 2022

Mobile Information Systems

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In order to solve the problem of extracting signals from impulse radio ultra-wideband (IR-UWB) receivers in a low signal-to-noise ratio (SNR) environment, this paper uses circuit transient analysis to establish a mathematical model of an ultra-wideband wireless communication receiver based on a balanced sampling and integration circuit (BSIC). The effect of receiver circuit component parameters on the output signal is simulated and tested, and the optimization of circuit component parameters for UWB wireless communication receivers is achieved. The sampling capacitance in the receiver circuit ranges from 1 pF to 6 pF, depending on the 200 ps pulse width. The output signal amplitude increases as the sampling capacitance increases. The range of integral capacitance is from 2.5 pF to 25 pF, which is based on a 100 ns interval between two pulses. The output signal amplitude decreases as the integration capacitance increases and the signal waveform becomes better as the integration capacitance increases. The effect of SNR from 0 to −30 dB on the receiver output is simulated, and the results show that the Bit Error Ratio (BER) of the receiver is less than 10−3 when the SNR is greater than −15 dB. The simulation and test results show that the model developed in this paper is useful as a guide for optimizing the receiver parameters at low SNR.

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Section: Introductionmentioning

confidence: 99%

Modeling and Simulation of Ultra-Wideband Communication Receiver Based on Balanced Sampling and Integrating Circuit

Wang

Huang

Hao

et al. 2022

Mobile Information Systems

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“…Given the characteristics and standards defined for wideband systems, CG‐based amplifiers can be introduced as a superior architecture 30 because their inherent features provide a wide range of input impedance matching and avoid off‐chip components. In CG LNA, input impedance matching is realized with more noise than LNA with an inductive impedance matching network.…”

Section: Introductionmentioning

confidence: 99%

A low‐power wideband LNA exploiting current‐reuse and noise cancelation techniques

Khanehbeygi

Jafarnejad

Koozehkanani

et al. 2022

Circuit Theory & Apps

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This paper presents an inductorless low-power wideband Low Noise Amplifier (LNA) in TSMC 0.18 μm CMOS technology. The proposed LNA is based on the Common-Gate (CG) topology, which consists of three consecutive stages: CG, Common-Source (CS), and Collector stage. The CG and CS configurations are responsible for providing the wideband input impedance matching and the majority of the gain, respectively. The overall performance of the LNA has been improved by applying noise cancelation, capacitive-peaking, and current reuse techniques. Unlike the conventional structure, the CG and CS sections' noise is canceled by utilizing a novel noise-canceling mechanism, simultaneously. Furthermore, with the capacitive-peaking technique, the voltage gain drop across hi gher frequencies is prevented, and thus, the bandwidth of the structure is improved. The trade-off between power consumption and input impedance has been dramatically resolved by employing the current reuse technique in the CG stage. Post-layout simulation results of the presented noise-canceling LNA demonstrate a Noise Figure (NF) of 2.19-2.58 dB and a maximum voltage gain of 19.84 dB with a À3 dB bandwidth of 0.2-2.85GHz. The simulated input/output matching (i.e., S11/S22) is better than À14.73/À19.43 dB in the entire bandwidth. Additionally, Input Third Intercept Point (IIP3) of À4.56 dBm is achieved. The results are gained by consuming only 2.87 mW under a supply voltage of 1.2 V and occupying a 0.0429 mm 2 of die area.

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