A variation-aware design for storage cells using Schottky-barrier-type GNRFETs

Abbasian, Erfan; Gholipour, Morteza

doi:10.1007/s10825-020-01529-y

Cited by 30 publications

(26 citation statements)

References 39 publications

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“…Read stability of an SRAM cell is gauged by RSNM, which is obtained by measuring the side length of the largest square that can be inserted inside the smaller lobe of the butterfly VTCs during read operation 33–35 . The FD8T shows the smallest RSNM as it is indeed a C6T cell, which leads to considerable read disturbance 13 .…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

“…As it can be seen from these figures, the SEHF11T shows 3.64X and 1.18X tighter spread than that of FD8T and HFBS9T or SEDF9T cells at V DD = 0.7 V, respectively. In other words, it has lower variability in terms of standard deviation ( σ ) over mean ( μ) ratio ( σ / μ ), 33 which indicates high reliability of SEHF11T under severe PVT variations.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

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Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

Abbasian

Gholipour

2021

Circuit Theory & Apps

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Summary This paper presents an 11 transistor (SEHF11T) static random access memory (SRAM) cell with high read static noise margin (RSNM) and write static noise margin (WSNM). It eliminates the write half‐select disturb using cross‐point data‐aware write word lines, which can mitigate bit‐interleaving structure to reduce multiple‐bit upset and increase soft‐error immunity. We evaluated and analyzed the effect of process, voltage, and temperature (PVT) variations on various design metrics and compared it with other cells. The SEHF11T performs fast read operation due to its higher read current and slow write operation due to its single‐ended nature. It employs the read decoupling technique to enhance the RSNM. The stacked transistors in the left/right half‐cell increase the RSNM. In addition, the WSNM is improved by eliminating the feedback of cross‐coupled inverters pair during write operation by means of power‐cutoff write‐assist technique. The proposed cell shows 1.11X higher RSNM and 1.37X higher WSNM compared to fully differential 8T (FD8T) cell. The stacked transistors in the cell reduce leakage power dissipation. The SEHF11T consumes 0.47X lower leakage power compared to FD8T at VDD = 0.7 V. Furthermore, it exhibits high reliability against PVT variations in subthreshold region and shows 1.09X narrower spread in leakage power than that of FD8T at VDD = 0.3 V.

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Section: Simulation Results and Discussionmentioning

confidence: 99%

Section: Simulation Results and Discussionmentioning

confidence: 99%

Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

Abbasian

Gholipour

2021

Circuit Theory & Apps

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“…5,11 GNRFETs are categorized into two types: (1) Schottky barrier (SB)-type having metal drain and source contacts and GNR-based channel and ( 2) MOSFET (MOS)-type with GNR-based drain, source, and channel. 6 We employ MOS-GNRFET (see Figure 1) to design the proposed SRAM cell due to its higher I on /I off than that of SB-GNRFET.…”

Section: The Gnrfet Devicementioning

confidence: 99%

“…nanoribbons (GNRFETs) [2][3][4][5][6] and transition metal dichalcogenide field-effect transistors (TMDFETs) [7][8][9][10] have emerged as potential alternatives devices due to their robust lattice structure and outstanding properties.…”

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confidence: 99%

Performance evaluation of GNRFET and TMDFET devices in static random access memory cells design

Abbasian

Gholipour

Izadinasab

2021

Circuit Theory & Apps

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Graphene nanoribbon and transition metal dichalcogenide field-effect transistors (GNRFETs and TMDFETs) have emerged as favorable candidates to replace conventional metal-oxide-semiconductor (MOS) transistor in future technologies. Their competence must be proven through the study and evaluation of various circuits, including static random access memories (SRAMs). Therefore, this paper presents a single-ended 12T (SE12T) SRAM cell designed using GNRFETs and TMDFETs to evaluate their performance. The proposed SE12T cell designed with GNRFETs/TMDFET device improves read static noise margin by 1.95Â/3.20Â and incurs a penalty of 1.16Â/1.14Â in read delay compared to the GNRFETs/TMDFET-based fully differential 8T cell through a read buffer, decoupling the bitline from the storing nodes during the read operation. Furthermore, two transmission gates (TGs) placed inside the cell core cut off the feedback of cross-coupled inverters pair during the write operation, enhancing write static noise margin by 1.65Â/1.71Â. These two TGs along with high logic level of virtual ground (V GND ) control signal during hold mode reduce leakage power. Existence of a higher number of p-type MOS (PMOS) devices, the presence of stacked transistors, and being single-ended bitcell further reduce this metric, nearly 1.48Â/1.17Â designed with GNRFETs/TMDFET device as compared to FD8T. Furthermore, it is observed from the results that GNRFET-based designs have better performance than those of their TMDFET counterparts. The proposed cell eliminates write half-select disturb, and therefore, bit-interleaving architecture can be applied to reduce multi-bit errors.

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“…SB-GNRFETs have a GNR-based channel and metalbased contacts, which SBs occur at the graphene-metal junctions. On the other hand, MOS-GNRFETs consist of a GNR-based channel and heavily doped source and drain reservoirs [13]. These doped reservoirs lead to a higher I ON /I OFF ratio and hence perform better than SB-GNRFETs.…”

Section: √3mentioning

confidence: 99%

Design of High-Performance 1-Bit Full Adder Cells Based on MOS-Type GNRFETs

Dehghan¹

2020

IJECEC

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In deep sub-micron technologies, conventional silicon-based transistors are faced main several problems related to the short-channel effects such as power dissipation, subthreshold leakage, and drain-induced barrier lowering (DIBL). Graphene nano-ribbon field-effect transistors (GNRFETs) have become a potential contender as a substitute for traditional silicon-based transistors in next generation nano-electronic devices. They exhibit fantastic properties such as high charge carrier mobility, mean free path of electrons, faster switching, and high ION/IOFF ratio. In order to prove the competences and superiority of these types of transistors, various circuits like full adder (FA) cells, which are the main building block of computational systems must be simulated and studied. This paper presents redesigning various 1-bit FA cells such as Complementary Metal-Oxide-Semiconductor (CMOS), Complementary Pass-Transistor Logic (CPL), Transmission-Gate (TG), Hybrid CMOS (HCMOS), and Transmission Function Adder (TFA) using MOS-GNRFET devices in 16nm technology node. Different HSPICE simulations are performed to obtain propagation delay, average power consumption, power-delay-product (PDP), and energy-delay-product (EDP) of FA cells and are compared with 16nm CMOS predictive technology model (PTM) at different supply voltages. The obtained results indicate that MOS-GNRFET based 1-bit FA cells have better performance than that of Si-CMOS one. The MOS-GNRFET based FA cells improve propagation delay and EDP at least 31.195% and 4.372%, respectively.

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A variation-aware design for storage cells using Schottky-barrier-type GNRFETs

Cited by 30 publications

References 39 publications

Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

Single‐ended half‐select disturb‐free 11T static random access memory cell for reliable and low power applications

Performance evaluation of GNRFET and TMDFET devices in static random access memory cells design

Design of High-Performance 1-Bit Full Adder Cells Based on MOS-Type GNRFETs

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