A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application

Abstract

Advancement in technology towards mobile computing and communication demands longer battery life, which mandates the low power design methodologies. In this paper, we have presented a novel low-power 8T flip-flop (FF) architecture, which has outsmarted the existing well-known dynamic, semi-dynamic and explicit pulsed flip-flops in terms of power and delay. The major ingredient of this architecture is a voltage keeper, which is incorporated to achieve reliable logic switching at the propagating nodes of the design. However, we have also come up with two new approaches of gated clock generation based on transmission gate (TG) and pass transistor logic (PTL) as a modification of LECTOR-based gating. These gating logics have proved themselves to be competent enough to reduce both the static and dynamic power dissipations and hence are employed to the proposed flip-flop to achieve further reduction in power than its nongated correspondent. The performance of this proposed gated flip-flop is tested in a finite state machine with its application in low-power serial adder design. All the simulations are carried out using 65-nm and 90-nm CMOS technologies with a power supply of 1.1[Formula: see text]V at 6.6[Formula: see text]GHz clock frequency. The gated FF saves 52.12%, 6.36% and 28.18% average power-using LECTOR, TG and PTLs, respectively, with respect to its nongated counterpart in 65-nm technology. The performance metrics of gated and nongated proposed designs are affirmed in the environment of commercialized CMOS foundry.

Power and area-efficient register designs involving EHO algorithm

“…As we have proposed SRs out of DFF, we have taken similar low-power DFFs for building register designs. They are named as follows: transmission gate SR developed from a conventional transmission gate FF (TGSR) (Zhang et al , 2011); topologically compressed SR made out of topologically compressed FF (TCSR) (Kawai et al , 2014); logic structure reduction technique SR developed from logic structure reduction technique FF (LRSR) (Lin et al , 2017); SR made from a dynamic FF designed by author Gago (GagoSR) (Gago et al , 1993); pulse-triggered SR from pulse-triggered FF (PTSR) (Karimi et al , 2018); lector-based clock gating SR developed from LBCG FF (LBCG-SR) (Bhattacharjee and Majumder, 2018); scan SR developed from Scan FF (SC-SR) (Razmdideh et al , 2015); 18 transistor SRs made from 18TFF (18TSR) (Cai et al , 2018); and implicit pulse-triggered FF with clock gating and pull-up control scheme SR developed from IP-CGPC FF (IP-CGPCSR) (Geng et al , 2016). …”

A low-power D flip flop integrated by metal oxide thin film transistors employing internal feedback control

“…It is well known that the DFF is commonly constructed using a transmission gate in CMOS technology [8], as well as other novel designs [9][10][11]. However, there are only n-type MO TFTs available for integrated circuits application.…”