A low-power D flip flop integrated by metal oxide thin film transistors employing internal feedback control

Abstract

The conventional D flip flop (DFF) consists of six pseudo-CMOS NOR gates integrated by monotype transistors. By analyzing the six logic states of the conventional DFF, it is found that the three-input NOR gate can be replaced by a new three-input NOR gate with a pull-up control signal and the pull-up control signal is connected to an output of another NOR gate. As a result, a new DFF is developed by using such an internal feedback control method. The static power consumption can be reduced by cutting off the dc path properly in the proposed DFF. For comparison, the conventional DFF and the proposed DFF are both fabricated by metal oxide thin film transistors with an etch stop layer structure on the basis of the same design parameters. Both the conventional DFF and the proposed DFF have the same function and both work using the negative edge triggered method. The measured power consumption of the proposed DFF is at least 13% less than that of the conventional DFF under the condition of a 20 kHz clock signal.

A glitch free variability resistant high speed and low power sense amplifier based flip flop for digital sequential circuits

“…There are several low power flip flop designs available [4][5][6][7][8][9][10][11][12][13][14], which includes the most commonly used master slave flip flops, pulse triggered flip flops and sense amplifier based flip flops. The master slave flip flop suffers from long setup time and since it also has two latch stages which requires several logics, the clock to Q delay may be relatively more.…”