A glitch free variability resistant high speed and low power sense amplifier based flip flop for digital sequential circuits

Abstract

In this work, a sense amplifier based flip flop (SAFF) is presented appropriate for high speed, high data activity and low power operations. The delay and power of the proposed flip flop have been considerably reduced as it uses a novel single-ended latch structure. The flip flop (FF) also achieves glitch free operation and can be operated and is functional at near-threshold voltage levels. SPICE simulations were carried out to do a comprehensive and quantifiable analysis between the presented architecture and formerly known architectures in 32 nm CMOS technology. The proposed design achieved a reduction of minimum 22.67% in power at nominal voltage. In terms of Power Delay Product (PDP), a reduction of 63.51% was observed. At 100 MHz clock frequency, the power dissipation was lowered by 30%. The proposed design at data activity of 100% consumes 28.24% less power whereas at activities of less than 12.5% it does not show significant improvements. However, the proposed design has an advantage in terms of speed and is 40% to 82% faster at nominal conditions and can also operate at wide supply voltage. It also has the second lowest transistor count and second lowest area. The power performance is verified by implementing the proposed design as a 4-bit shift register.

Power Energy and Power Area Product Simulation Analysis of Master-Slave Flip-Flop

“…Shah O.A. [28] addressed the speed decreases and power consumption at higher data activities in previous approaches by proposing a better sense amplifier-based flip-flop design for low-power and high-data activity circuits. A low overhead warning flipfloat for timer leak monitoring was proposed by Cantoro R. et al [29].…”