In this paper, we compared various different techniques of previously published Single Edge Triggered Flip Flops (SET FFs). Flip Flops are most essential elements in the design of sequential circuits. We did the comparison for their performance and power dissipation and have also compared the transistor count of each Flip Flop.

In this paper, a 3-bit frequency divider (FD) using a novel sense amplifier based flip-flop (SAFF) is presented and demonstrated. The delay in this design was meticulously improved resulting in better values of power delay product (PDP).The latching stage of the proposed design makes use of a novel single ended structure. Comparative analysis in 32 nm CMOS technology using T-SPICE revealed significant and quantitative differences between the proposed design and the existing designs. The PDP results were obtained for ±10% voltage variation, wide temperature range of -40 ℃ to 125 ℃ and at extreme corner cases. Results indicated that the PDP of the new design at nominal operating conditions decreased by minimum of 27.28% and maximum of 57.49%. The proposed design was also at par with available design in terms of area and power. The analysis on the FD proved the assertions that the proposed design is a feasible alternative for high performance applications.

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