2011 World Congress on Information and Communication Technologies 2011
DOI: 10.1109/wict.2011.6141447
|View full text |Cite
|
Sign up to set email alerts
|

Analysis of different techniques for low power Single Edge Triggered Flip Flops

Abstract: In this paper, we compared various different techniques of previously published Single Edge Triggered Flip Flops (SET FFs). Flip Flops are most essential elements in the design of sequential circuits. We did the comparison for their performance and power dissipation and have also compared the transistor count of each Flip Flop.

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1

Citation Types

0
1
0

Year Published

2013
2013
2023
2023

Publication Types

Select...
4
1
1

Relationship

0
6

Authors

Journals

citations
Cited by 6 publications
(1 citation statement)
references
References 11 publications
0
1
0
Order By: Relevance
“…1 using Khan et al (2011) describes about Power Personal Computing 603 Flip flop and Mathan et al (2013) describes about modified single edge triggered delay Flip flop, depicts such that it is efficient and reliable comparing all sorts of designs. It is basically a Master Slave flip flop structure and it consists of two data paths.…”
Section: Proposed Low Power Single Edge Triggered D-flip Flopmentioning
confidence: 99%
“…1 using Khan et al (2011) describes about Power Personal Computing 603 Flip flop and Mathan et al (2013) describes about modified single edge triggered delay Flip flop, depicts such that it is efficient and reliable comparing all sorts of designs. It is basically a Master Slave flip flop structure and it consists of two data paths.…”
Section: Proposed Low Power Single Edge Triggered D-flip Flopmentioning
confidence: 99%