A Versatile and Accurate Compact Model of Memristor With Equivalent Resistor Topology

Zhu, Rong; Chang, Sheng; Wang, Hao; Huang, Qijun; He, Jin; Yi, Fan

doi:10.1109/led.2017.2736006

Cited by 15 publications

(7 citation statements)

References 23 publications

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“…Limitations of Strukov's model including vacancy boundary exiting the device ends, incorrect current-voltage (I-V) curves at very low frequencies, unwieldy dependence on q(t) etc., are recognized. Zhu et al overcome the issue of ionboundary exiting device ends, by constraining w(t) to stay within device length D [19]. Hong et al operate the HP model without encroaching on violating regions [29].…”

Section: Background a Dual Variable Resistor Modelmentioning

confidence: 99%

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Logistic Function Based Memristor Model With Circuit Application

2019

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A new SPICE compatible memristor model is presented which is based on the solution to the well-known Logistic equation. Previously published first order function models are limited in their ability to elucidate the memristor's oscillatory and chaotic behavior. Fractional order models are not SPICE friendly although they are known to demonstrate chaos. The relationship between the logistic equation and its iterated map is used to show how the proposed model explains the memristor's oscillatory and chaotic characteristic. It emulates empirically observed ohmic and semiconducting response to temperature. The utility of the model is tested by implementing it in a novel reliability and power aware relaxation oscillator design. A methodical approach to estimating the oscillation frequency of such highly nonlinear circuitry is presented. Computed results are validated against the relaxation oscillator implemented in an LTSpice testbench.

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Section: Background a Dual Variable Resistor Modelmentioning

confidence: 99%

“…The continued relevance of modeling is evidenced by recent literature [17]- [19]. Modeling has received attention at various levels of abstraction ranging from vacancy migration [20], [21] to resistance modeling [22] and some that are computationally simple piecewise [23]…”

Section: Introductionmentioning

confidence: 99%

Logistic Function Based Memristor Model With Circuit Application

2019

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“…However, because of the inherent material property, the intrinsic variation in switching conductance is a major challenge for some applications such as non-volatile memory 22 . Cycle-to-cycle variation is deviation between target conductance and updated conductance when the same updating signal in different updating cycles is applied in a memristor, even when the initial conductance is the same 23 .The memristor-based crossbar arrays suffer from serious cycle-to-cycle variation especially when arrays are used in the neuromorphic computing system that the conductance of memristor needs to be updated innumerable times during the training and testing process [24][25][26][27][28] . In previous works, researchers proposed some solutions including three aspects to mitigate such impact of the cycle-to-cycle variation.…”

Section: Introductionmentioning

confidence: 99%

Level Scaling and Pulse Regulating Methods to Mitigate Cycle-to-cycle Variation in Memristor Based Learning System

Liao¹,

Fu²,

Wang³

2020

Preprint

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As a novel non-volatile device, the memristive crossbar array has already delivered many of its promises including low computation complexity, high energy efficiency, and high density for the neuromorphic computing. However, the intrinsic variability of switching behavior has been a major obstacle to their implementation. Here we report a model that experimentally demonstrates the natural stochasticity of cycle-to-cycle variations and quantifies it. In addition, we propose level scaling and pulse regulating methods to mitigate the adverse impact of cycle-to-cycle variations. The relationship of the level of conductance and cycle-to-cycle variation is studied, and experiment results show an optimal number of the levels to mitigate cycle-to-cycle variations in the system. Additionally, the system compresses the number of pulses when the conductance is updated by the pulse stimulus to reduce cycle-to-cycle variations, resulting in the great energy and latency reduction. This work paves the way for the adoption of memristors for more efficient applications for the era of the edge computing and Internet of Things (IoT).

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“…However, memristor has its limitations as a novel device. Still now, most memristors' fabrications [15][16][17][18][19] are not compatible with mainstream integrated circuit technique and have large fluctuations in parameters [20][21][22], which limit their applications in real tasks. Under these technique limitations, realizing memristive characteristics by mature circuit methods [23] becomes a practicable way.…”

Section: Introductionmentioning

confidence: 99%

A hardware friendly unsupervised memristive neural network with weight sharing mechanism

et al. 2019

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Memristive neural networks (MNNs), which use memristors as neurons or synapses, have become a hot research topic recently. However, most memristors are not compatible with mainstream integrated circuit technology and their stabilities in large-scale are not very well so far. In this paper, a hardware friendly MNN circuit is introduced, in which the memristive characteristics are implemented by digital integrated circuit. Through this method, spike timing dependent plasticity (STDP) and unsupervised learning are realized. A weight sharing mechanism is proposed to bridge the gap of network scale and hardware resource. Experiment results show the hardware resource is significantly saved with it, maintaining good recognition accuracy and high speed. Moreover, the tendency of resource increase is slower than the expansion of network scale, which infers our method's potential on large scale neuromorphic network's realization.Index Terms-memristive neural networks (MNNs), digital integrated circuit, spike timing-dependent plasticity (STDP), unsupervised learning, weight sharing mechanism

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A Versatile and Accurate Compact Model of Memristor With Equivalent Resistor Topology

Cited by 15 publications

References 23 publications

Logistic Function Based Memristor Model With Circuit Application

Logistic Function Based Memristor Model With Circuit Application

Level Scaling and Pulse Regulating Methods to Mitigate Cycle-to-cycle Variation in Memristor Based Learning System

A hardware friendly unsupervised memristive neural network with weight sharing mechanism

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